Datasheet

Analog-to-Digital Converter
Technical Data MC68HC912D60A — Rev. 3.1
364 Analog-to-Digital Converter Freescale Semiconductor
Finally, which result registers hold valid data can be tracked using the
conversion complete flags. Fast flag clear mode may or may not be
useful in a particular application to track valid data.
FRZ1, FRZ0 — Background Debug Freeze Enable
Background debug freeze function allows the ATD module to pause
when a breakpoint is encountered. Table 18-3 shows how FRZ1 and
FRZ0 determine the ATD’s response to a breakpoint. When BDM is
deasserted, the ATD module continues operating as it was before the
breakpoint occurred.
18.9.3 ATDCTL4 ATD Control Register 4
ATD control register 4 is used to select the internal ATD clock frequency
(based on the system clock), select the length of the third phase of the
sample period, and set the resolution of the A/D conversion (i.e. 8-bits or
10-bits). All writes to this register have an immediate effect. If a
conversion is in progress, the entire conversion sequence is aborted. A
write to this register (or ATDCTL5) initiates a new conversion sequence.
Table 18-3. ATD Response to Background Debug Enable
FRZ1 FRZ0 ATD Response
0 0 Continue conversions in active background mode
01 Reserved
1 0 Finish current conversion, then freeze
1 1 Freeze when BDM is active
ATD0CTL4/ATD1CTL4 — ATD Control Register 4 $0064/$01E4
Bit 7654321Bit 0
RES10 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0
RESET: 00000001