Datasheet

Analog-to-Digital Converter
Technical Data MC68HC912D60A — Rev. 3.1
366 Analog-to-Digital Converter Freescale Semiconductor
18.9.4 ATDCTL5 ATD Control Register 5
ATD control register 5 determines the type of conversion sequence and
the analog input channels sampled. All writes to this register have an
immediate effect. If a conversion is in progress, the entire conversion
sequence is aborted. A write to this register (or ATDCTL4) initiates a new
conversion sequence (SCF and CCF bits are reset).
S8C / S1C — Conversion Sequence Length
S8C: Bit Position: 6, ATDCTL5
S1C: Bit Position: 3, ATDCTL3
The S8C/S1C bits define the length of a conversion sequence. Table
18-6 lists the coding combinations.
Table 18-5. Clock Prescaler Values
Prescale
Value
Total Divisor
Max PCLK
(1)
1. Maximum conversion frequency is 2 MHz. Maximum PCLK divisor value will become
maximum conversion rate that can be used on this ATD module.
Min PCLK
(2)
2. Minimum conversion frequency is 500 kHz. Minimum PCLK divisor value will become
minimum conversion rate that this ATD can perform.
00000 ÷24 MHz 1 MHz
00001 ÷48 MHz 2 MHz
00010 ÷68 MHz 3 MHz
00011 ÷88 MHz 4 MHz
00100 ÷10 8 MHz 5 MHz
00101 ÷12 8 MHz 6 MHz
00110 ÷14 8 MHz 7 MHz
00111 ÷16 8 MHz 8 MHz
01xxx
Do Not Use
1xxxx
ATD0CTL5/ATD1CTL5 — ATD Control Register 5 $0065/$01E5
Bit 7654321Bit 0
0 S8C SCAN MULT SC CC CB CA
RESET: 00000000