Datasheet

Analog-to-Digital Converter
ATD Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Analog-to-Digital Converter 371
8 channel conversion, External channels (S8C = 1, SC = 0)
CC 0 0001111
CB 0 0110011
CA 0 1010101
ADR0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
ADR1 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN0
ADR2 AN2 AN3 AN4 AN5 AN6 AN7 AN0 AN1
ADR3 AN3 AN4 AN5 AN6 AN7 AN0 AN1 AN2
ADR4 AN4 AN5 AN6 AN7 AN0 AN1 AN2 AN3
ADR5 AN5 AN6 AN7 AN0 AN1 AN2 AN3 AN4
ADR6 AN6 AN7 AN0 AN1 AN2 AN3 AN4 AN5
ADR7 AN7 AN0 AN1 AN2 AN3 AN4 AN5 AN6
8 channel conversion, Internal Sources (S8C = 1, SC = 1)
CC 0 0001111
CB 0 0110011
CA 0 1010101
ADR0
VRH VRL MID
ADR1 VRH VRL MID
ADR2 VRH VRL MID
ADR3 VRH VRL MID
ADR4 VRH VRL MID
ADR5 VRL MID VRH
ADR6 MID
VRH VRL
ADR7
VRH VRL MID
Shaded cells are reserved
MID = (VRH + VRL) / 2
NOTES:
1) For compatibility with the 68HC912D60, CA, CB, CC bits must be ‘0’ where masked on the 68HC912D60. This is
shown above in bold text.
2) When MULT = 0, all four bits (SC, CC, CB, and CA) must be specified and a conversion sequence consists of four
or eight consecutive conversions of the single specified channel.
3) When S8C = 0 and S1C = 1, all four bits (SC, CC, CB, and CA) must be specified and a conversion sequence consists
of one conversion of the single specified channel.
Table 18-10. Multichannel Mode Result Register Assignment (MULT=1) (Continued)