Datasheet

Analog-to-Digital Converter
Technical Data MC68HC912D60A — Rev. 3.1
372 Analog-to-Digital Converter Freescale Semiconductor
18.9.5 ATDSTAT A/D Status Register
The ATD Status registers contain the conversion complete flags and the
conversion sequence counter. The status registers are read-only.
SCF — Sequence Complete Flag
This flag is set upon completion of a conversion sequence. If
conversion sequences are continuously performed (SCAN=1), the
flag is set after each one is completed. How this flag is cleared
depends on the setting of the fast flag clear bit. When AFFC=0, SCF
is cleared when a new conversion sequence is initiated (write to
register ATDCTL4/5). When AFFC=1, SCF is cleared after reading
the first (any) result register.
CC[2:0] — Conversion Counter
This 3-bit value represents the contents of the result register counter;
the result register counter points to the result register that will receive
the result of the current conversion. If not in FIFO mode, the register
counter is initialized to zero when a new conversion sequence is
begun.
If in FIFO mode, the register counter is not initialized. The result
register count wraps around when its maximum value is reached.
CCF[7:0] — Conversion Complete Flags
A conversion complete flag is set at the end of each conversion in a
conversion sequence. The flags are associated with the conversion
position in a sequence and the result register number. Therefore,
CCF0 is set when the first conversion in a sequence is complete and
ATD0STAT0/ATD1STAT0 — ATD Status Register $0066/$01E6
Bit 7654321Bit 0
SCF 0 0 0 0 CC2 CC1 CC0
RESET:00000000
ATD0STAT1/ATD1STAT1 — ATD Status Register $0067/$01E7
Bit 7654321Bit 0
CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
RESET: 0 0 0 0 0 0 0 0