Datasheet

Development Support
Background Debug Mode
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Development Support 381
BKGD pin during host-to-target transmissions to speed up rising edges.
Since the target does not drive the BKGD pin during this period, there is
no need to treat the line as an open-drain signal during host-to-target
transmissions.
Figure 19-1. BDM Host to Target Serial Bit Timing
Figure 19-2. BDM Target to Host Serial Bit Timing (Logic 1)
10 CYCLES
BDMCLK
(TARGET MCU)
HOST
TRANSMIT 1
TARGET SENSES BIT
EARLIEST
START OF
NEXT BIT
SYNCHRONIZATION
UNCERTAINTY
PERCEIVED
START
OF BIT TIME
HOST
TRANSMIT 0
10 CYCLES
BDMCLK
(TARGET
MCU)
EARLIEST
START OF
NEXT BIT
BKGD PIN
PERCEIVED
START OF BIT
TIME
10 CYCLES
HOST SAMPLES
BKGD PIN
HOST
DRIVE TO
BKGD PIN
TARGET MCU
SPEEDUP PULSE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
HIGH-IMPEDANCE