Datasheet

Development Support

Background Debug Mode

MC68HC912D60A — Rev. 3.1 Technical Data

Freescale Semiconductor Development Support 387

program other bits of the SHADOW byte (location $0FC0);

otherwise some regular EEPROM array locations will not be

visible. At the next reset, the SHADOW byte is loaded into the

EEMCR register. NOBDML bit in EEMCR will be cleared and BDM

will not be operational.

4. Protect the SHADOW byte by setting SHPROT bit in EEPROT

19.4.4.2 Disabling BDM lockout

Disabling the BDM lockout is only possible in special modes

(SMODN=0) except in special single chip mode. Follow the same steps

as for enabling the BDM lockout, but erase the SHADOW byte.

At the next reset, the SHADOW byte is loaded into the EEMCR register.

NOBDML bit in EEMCR will be set and BDM becomes operational.

NOTE: When the BDM lockout is enabled it is not possible to run code from the

reset vector in special single chip mode.

19.4.5 BDM Registers

Seven BDM registers are mapped into the standard 64-Kbyte address

space when BDM is active. Mapping is shown in Table 19-4.

• The INSTRUCTION register content is determined by the type of

background command being executed.

• The STATUS register indicates BDM operating conditions.

• The SHIFT register contains data being received or transmitted

via the serial interface.

Table 19-4. BDM registers

Address Register

$FF00 BDM Instruction Register

$FF01 BDM Status Register

$FF02 - $FF03 BDM Shift Register

$FF04 - $FF05 BDM Address Register

$FF06 BDM CCR Holding Register