Datasheet

Development Support
Technical Data MC68HC912D60A — Rev. 3.1
402 Development Support Freescale Semiconductor
These bits are compared to the most significant byte of the data bus or
the most significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the
breakpoint comparison.
These bits are compared to the least significant byte of the data bus or
the least significant byte of the address bus in dual address modes.
BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be
used in the breakpoint comparison.
19.6 Instruction Tagging
The instruction queue and cycle-by-cycle CPU activity can be
reconstructed in real time or from trace history that was captured by a
logic analyzer. However, the reconstructed queue cannot be used to
stop the CPU at a specific instruction, because execution has already
begun by the time an operation is visible outside the MCU. A separate
instruction tagging mechanism is provided for this purpose.
Executing the BDM TAGGO command configures two MCU pins for
tagging. The TAGLO
signal shares a pin with the LSTRB signal, and the
Bit 7654321Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
RESET: 0 0 0 0 0 0 0 0
BRKDH — Breakpoint Data Register, High Byte $0024
Bit 7654321Bit 0
Bit 7654321Bit 0
RESET: 0 0 0 0 0 0 0 0
BRKDL — Breakpoint Data Register, Low Byte $0025