Datasheet

Electrical Specifications
Tables of Data
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Electrical Specifications 413
NOTE: RESET is recognized during the first clock cycle it is held low. Internal
circuitry then drives the pin low for 16 clock cycles, releases the pin, and
samples the pin level 9 cycles later to determine the source of the
interrupt.
Table 20-12. Control Timing
Characteristic Symbol
8.0 MHz
Unit
Min Max
Frequency of operation
f
o
0.004 8.0 MHz
ECLK period
t
cyc
0.125 250 µs
External oscillator frequency
f
eo
0.5
16.0
(1)
MHz
Processor control setup time
t
PCSU
= t
cyc
/2 + 20
t
PCSU
82.5 —
ns
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be preempted by internal reset)
PW
RSTL
32
2
—
—
t
cyc
t
cyc
Mode programming setup time
t
MPS
4—
t
cyc
Mode programming hold time
t
MPH
10 — ns
Interrupt pulse width, IRQ
edge-sensitive mode
PW
IRQ
= 2t
cyc
+ 20
PW
IRQ
270 — ns
Wait recovery startup time
t
WRS
—4
t
cyc
Timer input capture pulse width
PW
TIM
= 2t
cyc
+ 20
PW
TIM
270 — ns
1. When using a quartz crystal, see Table 20-17 for allowable values.