Datasheet

Electrical Specifications
Tables of Data
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Electrical Specifications 419
Figure 20-6. Port Read Timing Diagram
Figure 20-7. Port Write Timing Diagram
Table 20-13. Peripheral Port Timing
Characteristic Symbol
8.0 MHz
Unit
Min Max
Frequency of operation (ECLK frequency)
f
o
0.004 8.0 MHz
ECLK period
t
cyc
0.125 250 µs
Peripheral data setup time
MCU read of portst
PDSU
= t
cyc
/2 + 40
t
PDSU
102 — ns
Peripheral data hold time
MCU read of ports
t
PDH
0—ns
Delay time, peripheral data write
MCU write to ports except Port CAN
t
PWD
—40ns
Delay time, peripheral data write
MCU write to Port CAN
t
PWD
—71ns
ECLK
MCU READ OF PORT
PORTS
t
PDSU
t
PDH
ECLK
MCU WRITE TO PORT
PREVIOUS PORT DATA NEW DATA VALID
PORT A
t
PWD