Datasheet

Electrical Specifications
Technical Data MC68HC912D60A — Rev. 3.1
420 Electrical Specifications Freescale Semiconductor
Table 20-14. Multiplexed Expansion Bus Timing
V
DD
= 5.0 Vdc ± 10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, unless otherwise noted
Num
Characteristic
(1), (2), (3), (4)
Delay Symbol
8 MHz
Unit
Min Max
Frequency of operation (ECLK frequency)
f
o
0.004 8.0 MHz
1
Cycle timet
cyc
= 1/f
o
—
t
cyc
0.125 250 µs
2
Pulse width, E lowPW
EL
= t
cyc
/2 + delay
−4
PW
EL
58 ns
3
Pulse width, E high
(5)
PW
EH
= t
cyc
/2 + delay
−2
PW
EH
60 ns
5
Address delay timet
AD
= t
cyc
/4 + delay
27
t
AD
50 ns
7
Address valid time to ECLK riset
AV
= PW
EL
− t
AD
—
t
AV
8ns
8
Multiplexed address hold timet
MAH
= t
cyc
/4 + delay
−18
t
MAH
13 ns
9 Address Hold to Data Valid —
t
AHDS
20 ns
10
Data Hold to High Zt
DHZ
= t
AD
− 20
—
t
DHZ
30 ns
11 Read data setup time —
t
DSR
25 ns
12 Read data hold time —
t
DHR
0ns
13 Write data delay time —
t
DDW
47 ns
14 Write data hold time —
t
DHW
20 ns
15
Write data setup time
(5)
t
DSW
= PW
EH
− t
DDW
—
t
DSW
13 ns
16
Read/write delay timet
RWD
= t
cyc
/4 + delay
18
t
RWD
49 ns
17
Read/write valid time to E riset
RWV
= PW
EL
− t
RWD
—
t
RWV
9ns
18 Read/write hold time —
t
RWH
20 ns
19
Low strobe
(6)
delay timet
LSD
= t
cyc
/4 + delay
18
t
LSD
49 ns
20
Low strobe
(6)
valid time to E riset
LSV
= PW
EL
− t
LSD
—
t
LSV
9ns
21
Low strobe
(6)
hold time
—
t
LSH
20 ns
22
Address access time
(5)
t
ACCA
= t
cyc
− t
AD
− t
DSR
—
t
ACCA
50 ns
23
Access time from E rise
(5)
t
ACCE
= PW
EH
− t
DSR
—
t
ACCE
35 ns
24
DBE delay from ECLK rise
(5)
t
DBED
= t
cyc
/4 + delay
8
t
DBED
39 ns
25
DBE
valid timet
DBE
= PW
EH
− t
DBED
—
t
DBE
21 ns
26 DBE
hold time from ECLK fall
t
DBEH
010ns
1. All timings are calculated for normal port drives.
2. Crystal input is required to be within 45% to 55% duty.
3. Reduced drive must be off to meet these timings.
4. Unequalled loading of pins will affect relative timing numbers.
5. This characteristic is affected by clock stretch.
Add N × t
cyc
where N = 0, 1, 2, or 3, depending on the number of clock stretches.
6. Without TAG enabled.