Datasheet

Electrical Specifications
Technical Data MC68HC912D60A — Rev. 3.1
422 Electrical Specifications Freescale Semiconductor
Table 20-15. SPI Timing
(V
DD
= 5.0 Vdc ±10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, 200 pF load on all SPI pins)
(1)
Num Function Symbol Min Max Unit
Operating Frequency
Master
Slave
f
op
f
eclk
/256
f
eclk
/256
4
4
MHz
1
SCK Period
Master
Slave
t
sck
2
2
256
—
t
cyc
t
cyc
2
Enable Lead Time
Master
Slave
t
lead
1/2
1
—
—
t
sck
t
cyc
3
Enable Lag Time
Master
Slave
t
lag
1/2
1
—
—
t
sck
t
cyc
4
Clock (SCK) High or Low Time
Master
Slave
t
wsck
t
cyc
− 30
t
cyc
− 30
128 t
cyc
—
ns
ns
5
Sequential Transfer Delay
Master
Slave
t
td
1/2
1
—
—
t
sck
t
cyc
6
Data Setup Time (Inputs)
Master
Slave
t
su
30
30
—
—
ns
ns
7
Data Hold Time (Inputs)
Master
Slave
t
hi
0
30
—
—
ns
ns
8
Slave Access Time
t
a
—1
t
cyc
9
Slave MISO Disable Time
t
dis
—1
t
cyc
10
Data Valid (after SCK Edge)
Master
Slave
t
v
—
—
50
50
ns
ns
11
Data Hold Time (Outputs)
Master
Slave
t
ho
0
0
—
—
ns
ns
12
Rise Time
Input
Output
t
ri
t
ro
—
—
t
cyc
− 30
30
ns
ns
13
Fall Time
Input
Output
t
fi
t
fo
—
—
t
cyc
− 30
30
ns
ns
1. All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.