Datasheet

Electrical Specifications
Tables of Data
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Electrical Specifications 425
Table 20-16. CGM Characteristics
V
DD
= 5.0 V dc ±10%, V
SS
= 0 V dc, T
A
= T
L
to T
H
Characteristic Symbol Min. Typ. Max. Unit
PLL reference frequency
f
REF
0.5 8 MHz
Bus frequency
f
BUS
0.004 8 MHz
VCO range
f
VCO
2.5 8 MHz
VCO Limp-Home frequency
f
VCOMIN
0.5 1
2.5
(1)
MHz
Lock Detector transition from Acquisition to
Tracking mode
(2)
∆
trk
3% 4% —
Lock Detection
∆
Lock
0% 1.5% —
Un-Lock Detection
∆
unl
0.5% 2.5% —
Lock Detector transition from Tracking to
Acquisition mode
(2)
∆
unt
6% 8% —
Minimum leakage resistance on crystal oscillator
pins
r
leak
1MΩ
On the K38K mask set
PLL Stabilization delay
(3)
PLL Total Stabilization Delay
(4)
t
stab
3ms
PLLON Acquisition mode stabilization delay.
(4)
t
acq
1ms
PLLON tracking mode stabilization delay.
(4)
t
al
2ms
1. On the K38K mask set, the limp home mode frequency is higher than the specified maximum limit.
2. AUTO bit set
3. PLL stabilization delay is highly dependent on operational requirement and external component values (i.e. crystal, XFC
filter component values|). Note (4) shows typical delay values for a typical configuration. Appropriate XFC filter values
should be chosen based on operational requirement of system.
4.
f
REF
= 4MHz, f
BUS
= 8MHz (REFDV = #$00, SYNR = #$01), XFC:Cs = 33nF, Cp = 3.3nF, Rs = 2.7KΩ.
Table 20-17. Oscillator Characteristics
MC68HC912D60A MC68HC912D60C MC68HC912D60P Unit
Input buffer hysteresis
(1)
Min
Max
0
50
75
350
75
350
mV
Resonator Frequency
(2)
(VDDPLL=VDD)
Min
Max
0.5
8
0.5
8
0.5
8
MHz
Resonator Frequency
(2)
(VDDPLL=0V)
Min
Max
4
10
4
10
0.5
16
MHz
1. These values are dervied from design simulation and are not tested
2. Specifications apply to quartz or ceramic resonators only