Datasheet

Appendix: CGM Practical Aspects
Practical Aspects For The PLL Usage
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Appendix: CGM Practical Aspects 431
Table 21-1. Suggested 8MHz Synthesis PLL Filter Elements (Tracking Mode)
Reference [MHz] SYNR Fbus [MHz] C [nF] R [kΩ]
Loop Bandwidth
[kHz]
Bandwidth
Limit [kHz]
0.614 $0C 7.98 100 4.3 1.1 157
0.614 $0C 7.98 4.7 20 5.3 157
0.614 $0C 7.98 1 43 11.5 157
0.614 $0C 7.98 0.33 75 20 157
0.8 $09 8.00 220 2.7 0.9 201
0.8 $09 8.00 10 12 4.2 201
0.8 $09 8.00 2.2 27 8.6 201
0.8 $09 8.00 0.47 56 19.2 201
1 $07 8.00 220 2.4 1 251
1 $07 8.00 10 11 4.7 251
1 $07 8.00 2.2 24 9.9 251
1 $07 8.00 0.47 51 21.4 251
1.6 $05 8.00 330 1.5 1 402
1.6 $05 8.00 10 9.1 5.9 402
1.6 $05 8.00 3.3 15 10.2 402
1.6 $05 8.00 1 27 18.6 402
2 $03 8.00 470 1.1 0.96 502
2 $03 8.00 22 5.1 4.4 502
2 $03 8.00 4.7 11 9.6 502
2 $03 8.00 1 24 20.8 502
2.66 $02 8.00 220 1.5 1.6 668
2.66 $02 8.00 22 4.7 5.1 668
2.66 $02 8.00 4.7 10 11 668
2.66 $02 8.00 1 22 24 668
4 $01 8.00 220 1.2 1.98 1005
4 $01 8.00 33 3 5.1 1005
4 $01 8.00 10 5.6 9.3 1005
4 $01 8.00 2.2 12 19.8 1005