Datasheet

Appendix: CGM Practical Aspects
Technical Data MC68HC912D60A — Rev. 3.1
432 Appendix: CGM Practical Aspects Freescale Semiconductor
Table 21-2. Suggested 8MHz Synthesis PLL Filter Elements (Acquisition Mode)
Reference [MHz] SYNR Fbus [MHz] C [nF] R [kΩ]
Loop Bandwidth
[kHz]
Bandwidth
Limit [kHz]
0.614 $0C 7.98 1000 0.43 1.2 157
0.614 $0C 7.98 47 2 5.5 157
0.614 $0C 7.98 10 4.3 12 157
0.614 $0C 7.98 3.3 7.5 21 157
0.8 $09 8.00 2200 0.27 0.9 201
0.8 $09 8.00 100 1.2 4.4 201
0.8 $09 8.00 22 2.4 9.3 201
0.8 $09 8.00 4.7 5.6 20.1 201
1 $07 8.00 2200 0.22 1 251
1 $07 8.00 100 1 4.8 251
1 $07 8.00 2. 2.2 10.4 251
1 $07 8.00 4.7 4.7 22.5 251
1.6 $05 8.00 3300 0.15 1.1 402
1.6 $05 8.00 100 0.82 6.2 402
1.6 $05 8.00 33 1.5 10.7 402
1.6 $05 8.00 10 2.7 19.5 402
2 $03 8.00 4700 0.1 1 502
2 $03 8.00 220 0.51 4.6 502
2 $03 8.00 47 1 10 502
2 $03 8.00 10 2.4 21.8 502
2.66 $02 8.00 2200 0.12 1.7 668
2.66 $02 8.00 220 0.43 5.3 668
2.66 $02 8.00 47 1 11.6 668
2.66 $02 8.00 10 2 25.1 668
4 $01 8.00 2200 0.1 2.1 1005
4 $01 8.00 330 0.27 5.4 1005
4 $01 8.00 100 0.51 9.7 1005
4 $01 8.00 22 1 20.8 1005