Datasheet

MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor List of Paragraphs 5
Technical Data — MC68HC912D60A
List of Paragraphs
List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Section 1. General Description . . . . . . . . . . . . . . . . . . . .23
Section 2. Central Processing Unit . . . . . . . . . . . . . . . . .31
Section 3. Pinout and Signal Descriptions . . . . . . . . . . .37
Section 4. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Section 5. Operating Modes and Resource Mapping . .71
Section 6. Bus Control and Input/Output . . . . . . . . . . . .85
Section 7. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . .97
Section 8. EEPROM Memory . . . . . . . . . . . . . . . . . . . . .105
Section 9. Resets and Interrupts . . . . . . . . . . . . . . . . . .119
Section 10. I/O Ports with Key Wake-up . . . . . . . . . . . .129
Section 11. Clock Functions . . . . . . . . . . . . . . . . . . . . .137
Section 12. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . .175
Section 13. Pulse Width Modulator . . . . . . . . . . . . . . . .207
Section 14. Enhanced Capture Timer . . . . . . . . . . . . . .223
Section 15. Multiple Serial Interface . . . . . . . . . . . . . . .263
Section 16. Freescale Interconnect Bus . . . . . . . . . . . .289