Datasheet

Bus Control and Input/Output
Registers
MC68HC912D60A — Rev. 3.1 Technical Data
Freescale Semiconductor Bus Control and Input/Output 87
Bits PA[7:0] are associated respectively with addresses ADDR[15:8],
DATA[15:8] and DATA[7:0], in narrow mode. When this port is not used
for external addresses such as in single-chip mode, these pins can be
used as general-purpose I/O. DDRA determines the primary direction of
each pin. This register is not in the on-chip map in expanded and
peripheral modes. Read and write anytime.
This register determines the primary direction for each port A pin when
functioning as a general-purpose I/O port. DDRA is not in the on-chip
map in expanded and peripheral modes. Read and write anytime.
0 = Associated pin is a high-impedance input
1 = Associated pin is an output
Bit 7654321Bit 0
Single Chip PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
RESET: — — — — — — — —
Expanded
& Periph:
ADDR15/
DATA15
ADDR14/
DATA14
ADDR13/
DATA13
ADDR12/
DATA12
ADDR11/
DATA11
ADDR10/
DATA10
ADDR9/
DATA9
ADDR8/
DATA8
Expanded
narrow
ADDR15/
DATA15/
DATA7
ADDR14/
DATA14/
DATA6
ADDR13/
DATA13/
DATA5
ADDR12/
DATA12/
DATA4
ADDR11/
DATA11/
DATA3
ADDR10/
DATA10/
DATA2
ADDR9/
DATA9/
DATA1
ADDR8/
DATA8/
DATA0
PORTA — Port A Register $0000
Bit 7654321Bit 0
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0
RESET: 00000000
DDRA — Port A Data Direction Register $0002