Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 112 (20x20) 16-Bit 8 MHz I/O number 69

MOTOROLA.COM/SEMICONDUCTORS

M68HC12

Microcontrollers

MC912DT128A/D

Rev. 4, 10/2003

MC68HC912DT128A

MC68HC912DG128A

Technical Data

MC68HC912DT128C

MC68HC912DG128C

MC68HC912DT128P

MC68HC912DG128P

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

Summary of content (478 pages)

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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MC68HC912DT128A MC68HC912DG128A MC68HC912DT128C MC68HC912DG128C MC68HC912DT128P MC68HC912DG128P Technical Data M68HC12 Microcontrollers MC912DT128A/D Rev. 4, 10/2003 MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MC68HC912DT128A MC68HC912DG128A MC68HC912DT128C MC68HC912DG128C MC68HC912DT128P MC68HC912DG128P Technical Data Rev 4.0 Motorola reserves the right to make changes without further notice to any products herein.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data MC68HC912DT128A — Rev 4.0 4 MOTOROLA For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A List of Paragraphs Technical Data — List of Paragraphs . . . . . . . . . . . . . . . . 5 Freescale Semiconductor, Inc... Technical Data — Table of Contents. . . . . . . . . . . . . . . . . 7 Technical Data — List of Figures . . . . . . . . . . . . . . . . . . 17 Technical Data — List of Tables . . . . . . . . . . . . . . . . . . . 21 Section 1. General Description . . . . . . . . . . . . . . . . . . . . 25 Section 2.
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Freescale Semiconductor, Inc. List of Paragraphs Section 17. Inter IC Bus . . . . . . . . . . . . . . . . . . . . . . . . . 301 Section 18. MSCAN Controller . . . . . . . . . . . . . . . . . . . . 325 Section 19. Analog-to-Digital Converter . . . . . . . . . . . . 367 Section 20. Development Support. . . . . . . . . . . . . . . . . 395 Section 21. Electrical Specifications. . . . . . . . . . . . . . . 421 Freescale Semiconductor, Inc... Section 22. Appendix: Changes from MC68HC912DG128 . . . . . . . . . .
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Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Table of Contents List of Paragraphs Freescale Semiconductor, Inc... Table of Contents List of Figures List of Tables Section 1. General Description 1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . .26 1.
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Freescale Semiconductor, Inc. Table of Contents 2.7 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Freescale Semiconductor, Inc... Section 3. Pinout and Signal Descriptions 3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.2 MC68HC912DT128A Pin Assignments in 112-pin QFP. . . . . . 41 3.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.4 Signal Descriptions . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Section 7. Bus Control and Input/Output 7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.3 Detecting Access Type from External Signals . . . . . . . . . . . .103 7.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Freescale Semiconductor, Inc... Section 8.
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Freescale Semiconductor, Inc. Table of Contents 9.8 Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . . 135 Freescale Semiconductor, Inc... Section 10. Resets and Interrupts 10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.3 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.
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Freescale Semiconductor, Inc. Table of Contents 12.7 System Clock Frequency Formulae . . . . . . . . . . . . . . . . . . . . 181 12.8 Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 12.9 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . .185 12.10 Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.11 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table of Contents 16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 16.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 16.4 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .278 16.5 Serial Peripheral Interface (SPI) . . .
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Freescale Semiconductor, Inc. Table of Contents 18.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 18.12 Programmer’s Model of Message Storage . . . . . . . . . . . . . . .346 18.13 Programmer’s Model of Control Registers . . . . . . . . . . . . . . . 351 Freescale Semiconductor, Inc... Section 19. Analog-to-Digital Converter 19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 19.2 Introduction . . . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Section 22. Appendix: Changes from MC68HC912DG128 22.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 22.2 Significant changes from the MC68HC912DG128 (non-suffix device)441 Freescale Semiconductor, Inc... Section 23. Appendix: CGM Practical Aspects 23.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447 23.2 Introduction . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... 24.12 Changes from first version (internal release, no revision number) to Rev 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . .475 MC68HC912DT128A — Rev 4.0 MOTOROLA Technical Data Table of Contents For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table of Contents Technical Data 16 MC68HC912DT128A — Rev 4.0 Table of Contents For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A List of Figures Figure Freescale Semiconductor, Inc... 1-1 1-2 2-1 3-1 3-2 3-3 3-4 3-5 6-1 6-2 11-1 12-1 12-2 12-3 12-4 12-5 12-6 12-7 12-8 12-9 13-1 13-2 13-3 13-4 14-1 14-2 14-3 15-1 15-2 Title MC68HC912DT128A Block Diagram . . . . . . . . . . . . . . . . . . . . 30 MC68HC912DG128A Block Diagram. . . . . . . . . . . . . . . . . . . . 31 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Figures Freescale Semiconductor, Inc... 15-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . .245 15-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . .246 15-5 Block Diagram for Port7 with Output compare / Pulse Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 15-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Figures 21-3 21-4 21-5 21-6 21-7 21-8 Freescale Semiconductor, Inc... 21-9 21-9 21-9 21-10 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .431 WAIT Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . 432 Interrupt Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Port Read Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .434 Port Write Timing Diagram . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... List of Figures Technical Data 20 MC68HC912DT128A — Rev 4.0 List of Figures For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A List of Tables Table Freescale Semiconductor, Inc... 1-1 1-2 2-1 2-2 3-1 3-2 3-3 3-4 4-1 5-1 6-1 6-2 6-3 6-4 6-5 6-6 7-1 9-1 9-2 9-3 9-4 10-1 10-2 12-1 12-2 12-3 12-4 12-5 Title Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Development Tools Ordering Information. . . . . . . . . . . . . . . . .33 M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . .38 Summary of Indexed Operations . . . .
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Freescale Semiconductor, Inc. List of Tables Freescale Semiconductor, Inc... 14-1 14-2 14-3 15-1 15-2 15-3 16-1 16-2 16-3 16-4 17-1 17-2 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 18-9 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 20-1 20-2 20-3 20-4 20-5 20-6 Technical Data 22 Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . . 230 PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . . 240 PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. List of Tables Breakpoint Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Breakpoint Address Range Control . . . . . . . . . . . . . . . . . . . . 416 Breakpoint Read/Write Control . . . . . . . . . . . . . . . . . . . . . . . . 418 Tag Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 Thermal Characteristics . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... List of Tables Technical Data 24 MC68HC912DT128A — Rev 4.0 List of Tables For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.3 Devices Covered in this Document. . . . . . . . . . . . . . . . . . . . . .26 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5 MC68HC912DT128A Block Diagram . . . . . . . . . . . . . . . . . . . . 30 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description 1.3 Devices Covered in this Document The MC68HC912DG128A device is similar to the MC68HC912DT128A, but it has only two MSCAN12 modules. The entire databook applies to both devices, except where differences are noted. The MC68HC912DT128C and MC68HC912DT128P are devices similar to the MC68HC912DT128A, but with different oscillator configurations.
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Freescale Semiconductor, Inc. General Description Features • Memory – 128K byte flash EEPROM, made of four 32K byte modules with 8K bytes protected BOOT section in each module – 2K byte EEPROM – 8K byte RAM with Vstby, made of two 4K byte modules. • Two Analog-to-digital converters – 2 times 8-channels, 10-bit resolution Freescale Semiconductor, Inc... • Three 1M bit per second, CAN 2.
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Freescale Semiconductor, Inc. General Description • 4 PWM channels with programmable period and duty cycle – 8-bit 4-channel or 16-bit 2-channel – Separate control for each pulse width and duty cycle – Center- or left-aligned outputs – Programmable clock select logic with a wide range of frequencies • Serial interfaces Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. General Description Features • 112-Pin TQFP package – Up to 67 general-purpose I/O lines on the MC68HC912DT128A (up to 69 on the MC68HC912DG128A), plus up to 18 input-only lines – 5.0V operation at 8 MHz • Development support – Single-wire background debug™ mode (BDM) Freescale Semiconductor, Inc... – On-chip hardware breakpoints MC68HC912DT128A — Rev 4.0 MOTOROLA Technical Data General Description For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. General Description 1.
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General Description MC68HC912DG128A Block Diagram 1.
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Freescale Semiconductor, Inc. General Description 1.7 Ordering Information Table 1-1. Device Ordering Information Ambient Temperature Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. General Description Ordering Information Table 1-2.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... General Description Technical Data 34 MC68HC912DT128A — Rev 4.0 General Description For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 2. Central Processing Unit 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.3 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Central Processing Unit 2.3 Programming Model CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations. 7 A 0 7 B 0 8-BIT ACCUMULATORS A & B Freescale Semiconductor, Inc... OR 15 D 0 16-BIT DOUBLE ACCUMULATOR D 15 IX 0 INDEX REGISTER X 15 IY 0 INDEX REGISTER Y 15 SP 0 STACK POINTER 15 PC 0 PROGRAM COUNTER CONDITION CODE REGISTER S X H I N Z V C Figure 2-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit Data Types Stack pointer (SP) points to the last stack location used. The CPU12 supports an automatic program stack that is used to save system context during subroutine calls and interrupts, and can also be used for temporary storage of data. The stack pointer can also be used in all indexed addressing modes. Program counter is a 16-bit register that holds the address of the next instruction to be executed.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit 2.5 Addressing Modes Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12 includes all of the addressing modes of the M68HC11 CPU as well as several new forms of indexed addressing. Table 2-1 is a summary of the available addressing modes. Table 2-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Central Processing Unit Indexed Addressing Modes 2.6 Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. The postbyte and extensions do the following tasks: • Specify which index register is used.
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Freescale Semiconductor, Inc. Central Processing Unit 2.7 Opcodes and Operands The CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Freescale Semiconductor, Inc... Only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 3. Pinout and Signal Descriptions 3.1 Contents 3.2 MC68HC912DT128A Pin Assignments in 112-pin QFP. . . . . . 41 3.3 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 3.4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.5 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.
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Freescale Semiconductor, Inc.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MC68HC912DG128A 112TQFP 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 PW2/PP2 PW1/PP1 PW0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 KWJ7/PJ7 KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4 VDD PK3 VSS IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 KWJ3/PJ3 KWJ2/PJ2 KWJ1/PJ1 KWJ0/PJ0 SMODN/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/
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Freescale Semiconductor, Inc. Pinout and Signal Descriptions 0.20 T L-M N 4X PIN 1 IDENT 0.20 T L-M N 4X 28 TIPS 112 J1 85 4X P J1 1 CL 84 VIEW Y 108X X X=L, M OR N G VIEW Y B L M B1 Freescale Semiconductor, Inc... V 28 AA J V1 57 29 F D 56 0.13 N M T BASE METAL L-M N SECTION J1-J1 ROTATED 90 ° COUNTERCLOCKWISE A1 S1 A S C2 C VIEW AB θ2 0.050 0.10 T 112X SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Power Supply Pins 3.3 Power Supply Pins MC68HC912DT128A power and ground pins are described below and summarized in Table 3-1. All power supply pins must be connected to appropriate supplies. On no account must any pins be left floating. 3.3.1 Internal Power (VDD) and Ground (VSS) Power is supplied to the MCU through VDD and VSS.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 3.3.5 VDDPLL, VSSPLL Provides operating voltage and ground for the Phase-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. NOTE: The VSSPLL pin should always be grounded even if the PLL is not used. The VDDPLL pin should not be left floating. It is recommended to connect the VDDPLL pin to ground if the PLL is not used. 3.3.6 XFC PLL loop filter.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Signal Descriptions 3.3.7 VSTBY Stand-by voltage supply to static RAM. Used to maintain the contents of RAM with minimal power when the rest of the chip is powered down. Table 3-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions NOTE: When selecting a crystal, it is recommended to use one with the lowest possible frequency in order to minimise EMC emissions. 3.4.1.2 External Oscillator Connections XTAL is the crystal output. The XTAL pin must be left unterminated when an external CMOS compatible clock input is connected to the EXTAL pin. The XTAL output is normally intended to drive only a crystal.
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Freescale Semiconductor, Inc. Pinout and Signal Descriptions Signal Descriptions output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes out of reset synchronously. This allows the part to reach a proper reset state even if the clocks have failed, while allowing synchronized operation when starting out of reset.
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Freescale Semiconductor, Inc. Pinout and Signal Descriptions vector ($FFFA:FFFB). If neither clock monitor fail nor COP timeout are pending, processing begins by fetching the normal reset vector ($FFFE:FFFF). 3.4.4 Maskable Interrupt Request (IRQ) Freescale Semiconductor, Inc... The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or levelsensitive triggering is program selectable (INTCR register).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Signal Descriptions 3.4.5 Nonmaskable Interrupt (XIRQ) The XIRQ input provides a means of requesting a nonmaskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR network.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 3.4.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0]) External bus pins share functions with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in expanded modes, the pins are used for the external buses. In expanded wide mode, ports A and B are used for multiplexed 16-bit data and address buses.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Signal Descriptions 3.4.11 Instruction Queue Tracking Signals (IPIPE1 and IPIPE0) IPIPE1 (PE6) and IPIPE0 (PE5) signals are used to track the state of the internal instruction queue. Data movement and execution state information is time-multiplexed on the two signals. Refer to Development Support. 3.4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 3.4.15 Clock generation module test (CGMTST) The CGMTST pin (PE6) is the output of the clocks tested when CGMTE bit is set in PEAR register. The PIPOE bit must be cleared for the clocks to be tested. 3.4.16 TEST This pin is used for factory test purposes. It is recommended that this pin is not connected in the application, but it may be bonded to 5.5 V max without issue. Never apply voltage higher than 5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Signal Descriptions Table 3-2. MC68HC912DT128A Signal Description Summary Pin Name Shared port Pin Number 112-pin Description Maskable interrupt request input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or levelsensitive triggering is program selectable (INTCR register).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Table 3-2. MC68HC912DT128A Signal Description Summary Pin Name Shared port SDA PIB6 KWJ[7:0] PJ[7:0] KWH[7:0] PH[7:0] Pin Number 112-pin Description I2C bus serial data line pin 8–11, Key wake-up and general purpose I/O; can cause an interrupt when an input 19–22 transitions from high to low or from low to high (KWPJ).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Port Signals Setting the RDPA bit in register RDRIV causes all port A outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Bus Control and Input/Output. 3.5.2 Port B Port B pins are used for address and data in expanded modes.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions general-purpose I/O. PEAR settings override DDRE settings. Because PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in the DDRE register makes the corresponding bit in port E an output; clearing a bit in the DDRE register makes the corresponding bit in port E an input. The default reset state of DDRE is all zeroes. When the PUPE bit in the PUCR register is set, PE[7,3,2,1,0] are pulled up.
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Freescale Semiconductor, Inc. Pinout and Signal Descriptions Port Signals Setting the RDPH bit in register RDRIV causes all port H outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Bus Control and Input/Output. 3.5.5 Port J Freescale Semiconductor, Inc... Port J pins are used for key wake-ups that can be used with the pins configured as inputs or outputs.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions for general purpose I/O. Port K bit 3 is used as a general purpose I/O pin only. The port data register is not in the address map during expanded and peripheral mode operation with EMK set. When it is in the map, port K can be read or written at anytime. Register DDRK determines whether each port K pin is an input or output. DDRK is not in the address map during expanded and peripheral mode operation with EMK set.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Port Signals 3.5.9 Port CAN0 The MSCAN0 uses two external pins, one input (RxCAN0) and one output (TxCAN0). The TxCAN0 output pin represents the logic level on the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state. RxCAN0 is on bit 0 of Port CAN0, TxCAN0 is on bit 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions 3.5.11 Port AD1 This port is an analog input interface to the analog-to-digital subsystem and used for general-purpose input. When analog-to-digital functions are not enabled, the port has eight general-purpose input pins, PAD1[7:0]. The ADPU bit in the ATD1CTL2 register enables the A/D function. Port AD1 pins are inputs; no data direction register is associated with this port.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Port Signals Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels. Levels are at normal drive capability after reset. The PWCTL register can be read or written anytime after reset. Refer to Pulse Width Modulator. 3.5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions When the PUPT bit in the TMSK2 register is set, all input pins are pulled up internally by an active pull-up device. Pullups are disabled after reset. Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels. Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime after reset. Refer to Enhanced Capture Timer. Table 3-3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Table 3-3. MC68HC912DT128A Port Description Summary Port Name Pin Numbers 112-pin Data Direction Register (Address) Port S PS[7:0] 96–89 In/Out DDRS ($00D7) Port T PT[7:0] 18–15, 7–4 In/Out DDRT ($00AF) Description Serial communications interfaces 1 and 0 and serial peripheral interface subsystems; or general-purpose I/O.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pinout and Signal Descriptions Table 3-4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 4. Registers 4.1 Contents 4.2 Register Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 4.2 Register Block The register block can be mapped to any 2K byte boundary within the standard 64K byte address space by manipulating bits REG[15:11] in the INITRG register. INITRG establishes the upper five bits of the register block’s 16-bit address.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 5. Operating Modes 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Operating Modes Table 5-1. Mode Selection BKGD 1 1 1 1 0 0 0 0 MODB 0 0 1 1 0 0 1 1 MODA 0 1 0 1 0 1 0 1 Mode Normal Single Chip Normal Expanded Narrow Reserved (Forced to Peripheral) Normal Expanded Wide Special Single Chip Special Expanded Narrow Special Peripheral Special Expanded Wide Port A G.P. I/O ADDR/DATA — ADDR/DATA G.P. I/O ADDR/DATA ADDR/DATA ADDR/DATA Port B G.P. I/O ADDR — ADDR/DATA G.P.
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Freescale Semiconductor, Inc. Operating Modes Operating Modes Normal Expanded Narrow Mode — This is a normal mode of operation in which the expanded bus is present with an 8-bit data bus. Ports A and B are used for the16-bit address bus. Port A is used as the data bus, multiplexed with addresses. In this mode, 16-bit data is presented one byte at a time, the high byte followed by the low byte. The address is automatically incremented on the second cycle. Freescale Semiconductor, Inc... 5.3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Operating Modes while the MCU is in special peripheral mode as internal bus conflicts between BDM and the external master can cause improper operation of both functions.
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Freescale Semiconductor, Inc. Operating Modes Operating Modes ESTR — E Clock Stretch Enable Determines if the E Clock behaves as a simple free-running clock or as a bus control signal that is active only for external bus cycles. ESTR is always one in expanded modes since it is required for address and data de-multiplexing and must follow stretched cycles. 0 = E never stretches (always free running). 1 = E stretches high during external access cycles and low during non-visible internal accesses (IVIS = 0).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Operating Modes EMK — Emulate Port K In single-chip mode PORTK and DDRK are always in the map regardless of the state of this bit. 0 = Port K and DDRK registers are in the memory map. Memory expansion emulation is disabled and all pins are general purpose I/O. 1 = In expanded or peripheral mode, PORTK and DDRK are removed from the internal memory map.
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Freescale Semiconductor, Inc. Operating Modes Background Debug Mode Once enabled, background mode can be made active by a serial command sent via the BKGD pin or execution of a CPU12 BGND instruction. While background mode is active, the CPU can interpret special debugging commands, and read and write CPU registers, peripheral registers, and locations in memory. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Operating Modes Technical Data 86 MC68HC912DT128A — Rev 4.0 Operating Modes For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 6. Resource Mapping 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3 Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . .87 6.4 Flash EEPROM mapping through internal Memory Expansion 92 6.5 Miscellaneous System Control Register . . . . . . . . . . . . . . . . . . 96 6.6 Mapping test registers . . . .
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Freescale Semiconductor, Inc. Resource Mapping unintended operations, a write to one of these registers should be followed with a NOP instruction. Freescale Semiconductor, Inc... If conflicts occur when mapping resources, the register block will take precedence over the other resources; RAM or EEPROM addresses occupied by the register block will not be available for storage. When active, BDM ROM takes precedence over other resources, although a conflict between BDM ROM and register space is not possible.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping Internal Resource Mapping 6.3.1 Register Block Mapping After reset the 1K byte register block resides at location $0000 but can be reassigned to any 2K byte boundary within the standard 64K byte address space. Mapping of internal registers is controlled by five bits in the INITRG register. The register block occupies the first 1K byte of the 2K byte block.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping 6.3.2 RAM Mapping The MC68HC912DT128A has 8K bytes of fully static RAM that is used for storing instructions, variables, and temporary data during program execution. Since the RAM is actually implemented with two 4K RAM arrays, any misaligned word access between last address of first 4K RAM and first address of second 4K RAM will take two cycles instead of one.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping Internal Resource Mapping 6.3.3 EEPROM Mapping The MC68HC912DT128A has 2K bytes of EEPROM which is activated by the EEON bit in the INITEE register. Mapping of internal EEPROM is controlled by four bits in the INITEE register. After reset EEPROM address space begins at location $0800 but can be mapped to any 4K byte boundary within the standard 64K byte address space.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping 6.4 Flash EEPROM mapping through internal Memory Expansion The Page Index register or PPAGE provides memory management for the MC68HC912DT128A. PPAGE consists of three bits to indicate which physical location is active within the windows of the MC68HC912DT128A. The MC68HC912DT128A has a user’s program space window, a register space window for Flash module registers, and a test program space window.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping Flash EEPROM mapping through internal Memory Expansion Table 6-2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping 6.4.3 Test mode Program space expansion In special mode and for test purposes only, the 128K bytes of Flash EEPROM for MC68HC912DT128A can be accessed through a test program space window of 32K bytes. This window replaces the user’s program space window to be able to access an entire array. In special mode and with ROMTST bit set in MISC register, a program space is located from $8000 to $FFFF.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping Flash EEPROM mapping through internal Memory Expansion When inputs, these pins can be selected to be high impedance or pulled up. ECS — Emulation Chip Select of selected program space When this signal is active low it indicates that the program space is accessed. This also applies to test mode program space. An access is made if address is at the program space window and either the Flash or external memory is accessed.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping PPAGE — (Program) Page Index Register $00FF Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 PIX2 PIX1 PIX0 0 0 0 0 0 0 0 0 RESET: Read and write: anytime. This register determines the active page viewed through MC68HC912DT128A windows. CALL and RTC instructions have a special single wire mechanism to read and write this register without using an address bus. 6.
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Freescale Semiconductor, Inc. Resource Mapping Miscellaneous System Control Register NDRF — Narrow Data Bus for Register-Following Map Space Freescale Semiconductor, Inc... This bit enables a narrow bus feature for the 1K byte RegisterFollowing Map. This is useful for accessing 8-bit peripherals and allows 8-bit and 16-bit external memory devices to be mixed in a system. In Expanded Narrow (eight bit) modes, Single Chip Modes, and Peripheral mode, this bit has no effect.
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Freescale Semiconductor, Inc. Resource Mapping Table 6-6. EXSTR Stretch Bit Definition EXSTR1 EXSTR0 0 0 1 1 0 1 0 1 Number of E Clocks Stretched 0 1 2 3 Freescale Semiconductor, Inc... ROMHM — Flash EEPROM only in second Half of Map This bit has no meaning if ROMON bit is clear. 0 = The 16K byte of fixed Flash EEPROM in location $4000-$7FFF can be accessed. 1 = Disables direct access to 16K byte Flash EEPROM from $4000-$7FFF in the memory map.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resource Mapping Mapping test registers 6.6 Mapping test registers These registers are used in for testing the mapping logic. They can only be read and after each read they get cleared. A write to each register will have no effect.
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Freescale Semiconductor, Inc. Resource Mapping 6.7 Memory Maps The following diagrams illustrate the memory map for each mode of operation immediately after reset. $0000 $03FF $0000 $0400 $0800 $0FFF Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Resource Mapping Technical Data 102 MC68HC912DT128A — Rev 4.0 Resource Mapping For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 7. Bus Control and Input/Output 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 7.3 Detecting Access Type from External Signals . . . . . . . . . . . .103 7.4 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 7.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Bus Control and Input/Output Table 7-1. Access Type vs.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Bus Control and Input/Output Registers (R/W), IRQ, and XIRQ. When the associated pin is not used for one of these specific functions, the pin can be used as general-purpose I/O. The port E assignment register (PEAR) selects the function of each pin. DDRE determines the primary direction of each port E pin when configured to be general-purpose I/O. Some of these pins have software selectable pull-ups (DBE, LSTRB, R/W, IRQ and XIRQ).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers In peripheral mode, the PEAR register is not accessible for reads or writes. However, the CGMTE control bit is reset to one to configure PE6 as a test output for the CGM module. NDBE — No Data Bus Enable Freescale Semiconductor, Inc... Normal: write once; Special: write anytime EXCEPT the first. Read anytime. 0 = PE7 is used for DBE, external control of data enable on memories, or inverted E clock.
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Freescale Semiconductor, Inc. Bus Control and Input/Output 0 = PE4 is the external E-clock pin subject to the following limitation: In single-chip modes, to get an E clock output signal, it is necessary to have ESTR = 0 in addition to NECLK = 0. A 16-bit write to PEAR and MODE registers can configure all three bits in one operation. 1 = PE4 is a general-purpose I/O pin. LSTRE — Low Strobe (LSTRB) Enable Freescale Semiconductor, Inc... Normal: write once; Special: write anytime EXCEPT the first time.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Bus Control and Input/Output Registers CALE — Calibration Reference Enable Read and write anytime. 0 = Calibration reference is disabled and PE7 is general purpose I/O in single chip or peripheral modes or if NDBE bit is set. 1 = Calibration reference is enabled on PE7 in single chip and peripheral modes or if NDBE bit is set. DBENE — DBE or Inverted E Clock on PE7 Normal modes: write once. Special modes: write anytime EXCEPT the first time.
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Freescale Semiconductor, Inc. Bus Control and Input/Output PUPJ — Pull-Up or Pull-Down Port J Enable 0 = Port J resistive loads (pull-ups or pull-downs) are disabled. 1 = Enable resistive load devices (pull-ups or pull-downs) for all port J input pins. PUPH — Pull-Up or Pull-Down Port H Enable 0 = Port H resistive loads (pull-ups or pull-downs) are disabled. 1 = Enable resistive load devices (pull-ups or pull-downs) for all port H input pins. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Bus Control and Input/Output Registers RDRIV — Reduced Drive of I/O Lines RESET: Bit 7 RDPK 0 6 RDPJ 0 5 RDPH 0 $000D 4 RDPE 0 3 0 0 2 0 0 1 RDPB 0 Bit 0 RDPA 0 Freescale Semiconductor, Inc... These bits select reduced drive for the associated port pins. This gives reduced power consumption and reduced RFI with a slight increase in transition time (depending on loading). The reduced drive function is independent of which function is being used on a particular port.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Bus Control and Input/Output Technical Data 114 MC68HC912DT128A — Rev 4.0 Bus Control and Input/Output For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 8. Flash Memory 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 8.4 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . .116 8.5 Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 8.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash Memory 8.3 Overview Each 32K Flash EEPROM array is arranged in a 16-bit configuration and may be read as either bytes, aligned words or misaligned words. Access time is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations. The Flash EEPROM module supports bulk erase only. Each Flash EEPROM module has hardware interlocks which protect stored data from accidental corruption.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash Memory Flash EEPROM Registers fixed 32K Flash EEPROM array 11FEE32K. In expanded modes, the Flash EEPROM arrays are turned off. See Operating Modes. 8.6 Flash EEPROM Registers Each 32K byte Flash EEPROM module has a set of registers. The register space $00F4-$00F7 is in a register space window of four pages. Each register page of four bytes maps the register space for each Flash module and each page is selected by the PPAGE register.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash Memory BOOTP — Boot Protect The boot blocks are located at $E000–$FFFF and $A000–$BFFF for odd program pages for each Flash EEPROM module. Since boot programs must be available at all times, the only useful boot block is at $E000–$FFFF location. All paged boot blocks can be used as protected program space if desired.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash Memory Operation PGM — Program Control This bit configures the memory for program operation. PGM is interlocked with the ERAS bit such that both bits cannot be equal to 1 or set to1 at the same time. 0 = Program operation is not selected. 1 = Program operation selected. 8.7 Operation The Flash EEPROM can contain program and data.
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Freescale Semiconductor, Inc. Flash Memory Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed tFPGM maximum (40µs). 8.8 Programming the Flash EEPROM Freescale Semiconductor, Inc... Programming the Flash EEPROM is done on a row basis.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Flash Memory Erasing the Flash EEPROM 12. After time, tRCV (min 1µs), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed. For minimum overall programming time and least program disturb effect, the sequence should be part of an intelligent operation which iterates per row. 8.
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Freescale Semiconductor, Inc. Flash Memory 8.11 Flash protection bit FPOPEN The FPOPEN bit is located in EEMCR – EEPROM Module Configuration Register, bit 4. FPOPEN – Opens the Flash array for program or erase 0 = The whole Flash array is protected. 1 = The whole Flash array is enabled for program or erase FPOPEN can be read at anytime. Freescale Semiconductor, Inc... FPOPEN can be written only to ’0’ for protection but not to ’1’ for unprotect in normal mode.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 9. EEPROM Memory 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.3 EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . .124 9.4 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .125 9.5 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.
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Freescale Semiconductor, Inc. EEPROM Memory 9.3 EEPROM Selective Write More Zeros The EEPROM can be programmed such that one or multiple bits are programmed (written to a logic “0”) at a time. However, the user should never program any bit more than once before erasing the entire byte. In other words, the user is not allowed to over write a logic “0” with another “0’. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. EEPROM Memory EEPROM Programmer’s Model 9.4 EEPROM Programmer’s Model The EEPROM module consists of two separately addressable sections. The first is an eight-byte memory mapped control register block used for control, testing and configuration of the EEPROM array. The second section is the EEPROM array itself. At reset, the eight-byte register section starts at address $00EC and the EEPROM array is located from addresses $0800 to $0FFF.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. EEPROM Memory A steady internal self-time clock is required to provide accurate counts to meet EEPROM program/erase requirements. This clock is generated via by a programmable 10-bit prescaler register. Automatic program/erase termination is also provided. In ordinary situations, with crystal operating properly, the steady internal self-time clock is derived from the input clock source (EXTALi). The divider value is as in EEDIVH:EEDIVL.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. EEPROM Memory EEPROM Control Registers EEDIV[9:0] — Prescaler divider Loaded from SHADOW word at reset. Read anytime. Write once in normal modes (SMODN =1) if EELAT = 0 and anytime in special modes (SMODN =0) if EELAT = 0. The prescaler divider is required to produce a self-time clock with a fixed frequency around 28.6 Khz for the range of oscillator frequencies.
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Freescale Semiconductor, Inc. EEPROM Memory EEMCR — EEPROM Module Configuration RESET: Bit 7 6 NOBDML NOSHW —(3) —(3) $00F0 5 Reserved —(3) 4 (1) (2) FPOPEN —(3) 3 2 1 Bit 0 1 EESWAI PROTLCK DMY 1 1 0 0 1. Bit 5 has a test function and should not be programmed. 2. The FPOPEN bit is available only on the 0L05H and later mask sets. For previous masks, this bit is reserved. 3. Loaded from SHADOW word. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. EEPROM Memory EEPROM Control Registers FPOPEN — Opens the Flash Block for Program or Erase 0 = The whole Flash array is protected. 1 = The whole Flash array is enable for program or erase. Loaded from SHADOW word at reset. Read anytime. Write anytime in special modes (SMODN=0). Write once ’0’ is allowed in normal mode. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. EEPROM Memory EEPROT — EEPROM Block Protect RESET: Bit 7 SHPROT 1 6 1 1 $00F1 5 BPROT5 1 4 BPROT4 1 3 BPROT3 1 2 BPROT2 1 1 BPROT1 1 Bit 0 BPROT0 1 Prevents accidental writes to EEPROM. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. Freescale Semiconductor, Inc... SHPROT — SHADOW Word Protection 0 = The SHADOW word can be programmed and erased. 1 = The SHADOW word is protected from being programmed and erased.
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Freescale Semiconductor, Inc. EEPROM Memory EEPROM Control Registers . EEPROG — EEPROM Control RESET: Bit 7 BULKP 1 6 0 0 $00F3 5 AUTO 0 4 BYTE 0 3 ROW 0 2 ERASE 0 1 EELAT 0 Bit 0 EEPGM 0 BULKP — Bulk Erase Protection 0 = EEPROM can be bulk erased. 1 = EEPROM is protected from being bulk or row erased. Freescale Semiconductor, Inc... Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. AUTO — Automatic shutdown of program/erase operation.
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Freescale Semiconductor, Inc. EEPROM Memory ERASE — Erase Control 0 = EEPROM configuration for programming. 1 = EEPROM configuration for erasure. Read anytime. Write anytime if EEPGM = 0. Configures the EEPROM for erasure or programming. Unless BULKP is set, erasure is by byte, aligned word, row or bulk. Freescale Semiconductor, Inc... EELAT — EEPROM Latch Control 0 = EEPROM set up for normal reads. 1 = EEPROM address and data bus latches set up for programming or erasing. Read anytime.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. EEPROM Memory Program/Erase Operation 9.6 Program/Erase Operation A program or erase operation should follow the sequence below if AUTO bit is clear: 1. Write BYTE, ROW and ERASE to desired value, write EELAT = 1 2. Write a byte or an aligned word to an EEPROM address 3. Write EEPGM = 1 4. Wait for programming, tPROG or erase, tERASE delay time 5. Write EEPGM = 0 6.
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Freescale Semiconductor, Inc. EEPROM Memory 9.7 Shadow Word Mapping The shadow word is mapped to location $_FC0 and $_FC1 when the NOSHW bit in EEMCR register is zero. The value in the shadow word is loaded to the EEMCR, EEDIVH and EEDIVL after reset. Table 9-4 shows the mapping of each bit from shadow word to the registers. Freescale Semiconductor, Inc... Table 9-4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. EEPROM Memory Programming EEDIVH and EEDIVL Registers 9.8 Programming EEDIVH and EEDIVL Registers The EEDIVH and EEDIVL registers must be correctly set according to the oscillator frequency before any EEPROM location can be programmed or erased. 9.8.1 Normal mode The EEDIVH and EEDIVL registers are write once in normal mode.
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Freescale Semiconductor, Inc. EEPROM Memory 5. Program bits 1 and 0 of the high byte of the SHADOW word and bits 7 to 0 of the low byte of the SHADOW word like a regular EEPROM location at address $0FC0 and $0FC1. Do not program other bits of the high byte of the SHADOW word (location $0FC0); otherwise some regular EEPROM array locations will not be visible. At the next reset, the SHADOW values are loaded into the EEDIVH and EEDIVL registers.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 10. Resets and Interrupts 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.3 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4 Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 10.5 Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts 10.3 Exception Priority A hardware priority hierarchy determines which reset or interrupt is serviced first when simultaneous requests are made. Six sources are not maskable. The remaining sources are maskable, and any one of them can be given priority over other maskable interrupts. The priorities of the non-maskable sources are: 1. POR or RESET pin 2. Clock monitor reset 3. COP watchdog reset 4.
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Freescale Semiconductor, Inc. Resets and Interrupts Latching of Interrupts 10.5 Latching of Interrupts XIRQ is always level triggered and IRQ can be selected as a level triggered interrupt. These level triggered interrupt pins should only be released during the appropriate interrupt service routine. Generally the interrupt service routine will handshake with the interrupting logic to release the pin.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts Table 10-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts Interrupt Control and Priority Registers Table 10-1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts IRQEN can be read and written anytime in all modes. DLY — Enable Oscillator Start-up Delay on Exit from STOP The delay time of about 4096 cycles is based on the XCLK rate chosen. 0 = No stabilization delay imposed on exit from STOP mode. A stable external oscillator must be supplied. 1 = Stabilization delay is imposed before processing resumes after STOP. DLY can be read anytime and written once in normal modes.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts Resets These registers can only be read in special modes (read in normal mode will return $00). Reading these registers at the same time as the interrupt is changing will cause an indeterminate value to be read. These registers can only be written in special mode.
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Freescale Semiconductor, Inc. Resets and Interrupts source of reset in a system. The POR circuit only initializes internal circuitry during cold starts and cannot be used to force a reset as system voltage drops. It is important to use an external low voltage reset circuit (for example: MC34064 or MC33464) to prevent power transitions or corruption of RAM or EEPROM. Freescale Semiconductor, Inc... 10.8.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts Effects of Reset software failing to execute the sequence properly causes a COP reset to occur. In addition, windowed COP operation can be selected. In this mode, a write to the COPRST register must occur in the last 25% of the selected period. A premature write will also reset the part. 10.8.4 Clock Monitor Reset If clock frequency falls below a predetermined limit when the clock monitor is enabled, a reset occurs. 10.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Resets and Interrupts 10.9.3 Interrupts PSEL is initialized in the HPRIO register with the value $F2, causing the external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin is configured for level-sensitive operation (for wired-OR systems). However, the interrupt mask bits in the CPU12 CCR are set to mask Xand I-related interrupt requests. 10.9.
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Freescale Semiconductor, Inc. Resets and Interrupts Register Stacking 10.9.7 Other Resources The enhanced capture timer (ECT), pulse width modulation timer (PWM), serial communications interfaces (SCI0 and SCI1), serial peripheral interface (SPI), inter-IC bus (IIC), Motorola Scalable CANs (MSCAN0 and MSCAN1) and analog-to-digital converters (ATD0 and ATD1) are off after reset. Freescale Semiconductor, Inc... 10.
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Freescale Semiconductor, Inc. Resets and Interrupts Freescale Semiconductor, Inc... If another interrupt is pending at the end of an interrupt service routine, the register unstacking and restacking is bypassed and the vector of the interrupt is fetched. Technical Data 148 MC68HC912DT128A — Rev 4.0 Resets and Interrupts For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 11. I/O Ports with Key Wake-up 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 11.3 Key Wake-up and port Registers . . . . . . . . . . . . . . . . . . . . . . 150 11.4 Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.2 Introduction The offers 16 additional I/O ports with key wake-up capability.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up 11.3 Key Wake-up and port Registers PORTJ — Port J Register $0028 Bit 7 6 5 4 3 2 1 Bit 0 PORT PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 KWU KWJ7 KWJ6 KWJ5 KWJ4 KWJ3 KWJ2 KWJ1 KWJ0 RESET: - - - - - - - - Read and write anytime.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up Key Wake-up and port Registers DDRH — Port H Data Direction Register RESET: $002B Bit 7 6 5 4 3 2 1 Bit 0 DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 0 0 0 0 0 0 0 0 Data direction register H is associated with port H and designates each pin as an input or output. Read and write anytime.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up KWIFJ — Key Wake-up Port J Flag Register $002E Bit 7 6 5 4 3 2 1 Bit 0 KWIFJ7 KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJ0 0 0 0 0 0 0 0 0 RESET: Read and write anytime. Each flag is set by an active edge on its associated input pin. This could be a rising or falling edge based on the state of the KWPJ register. To clear the flag, write one to the corresponding bit in KWIFJ.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up Key Wake-up and port Registers KWPJ — Key Wake-up Port J Polarity Register RESET: $0030 Bit 7 6 5 4 3 2 1 Bit 0 KWPJ7 KWPJ6 KWPJ5 KWPJ4 KWPJ3 KWPJ2 KWPJ1 KWPJ0 0 0 0 0 0 0 0 0 Read and write anytime. It is best to clear the flags after initializing this register because changing the polarity of a bit can cause the associated flag to become set.
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Freescale Semiconductor, Inc. I/O Ports with Key Wake-up 11.4 Key Wake-Up Input Filter The KWU input signals are filtered by a digital filter which is active only during STOP mode. The purpose of the filter is to prevent single pulses shorter than a specified value from waking the part from STOP. Freescale Semiconductor, Inc... The filter is composed of an internal oscillator and a majority voting logic.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. I/O Ports with Key Wake-up Key Wake-Up Input Filter Glitch, filtered out, no STOP wake-up Valid STOP Wake-Up pulse tKWSTP min. tKWSTP max. Minimum time interval between pulses to be recognized as single pulses tKWSP Figure 11-1. STOP Key Wake-up Filter MC68HC912DT128A — Rev 4.0 MOTOROLA Technical Data I/O Ports with Key Wake-up For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... I/O Ports with Key Wake-up Technical Data 156 MC68HC912DT128A — Rev 4.0 I/O Ports with Key Wake-up For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 12. Clock Functions 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 12.4 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.5 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Clock Functions 12.3 Clock Sources A compatible external clock signal can be applied to the EXTAL pin or the MCU can generate a clock signal using an on-chip oscillator circuit and an external crystal or ceramic resonator. The MCU uses several types of internal clock signals derived from the primary clock signal: TxCLK clocks are used by the CPU. Freescale Semiconductor, Inc... ECLK and PCLK are used by the bus interfaces, SPI, PWM, ATD0 and ATD1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Phase-Locked Loop (PLL) T1CLK T2CLK T3CLK T4CLK INT ECLK PCLK XCLK CANCLK Figure 12-1. Internal Clock Relationships 12.4 Phase-Locked Loop (PLL) The phase-locked loop (PLL) of the MC68HC912DT128A is designed for robust operation in an Automotive environment. The allowed PLL crystal or ceramic resonator reference of 0.
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Freescale Semiconductor, Inc. Clock Functions EXTAL REDUCED CONSUMPTION OSCILLATOR REFERENCE PROGRAMMABLE DIVIDER LOCK LOCK DETECTOR REFDV <2:0> REFCLK XTAL EXTALi DIVCLK PDET PHASE DETECTOR UP DOWN CPUMP VCO VDDPLL Freescale Semiconductor, Inc... SLOW MODE PROGRAMMABLE CLOCK DIVIDER SLWCLK LOOP PROGRAMMABLE DIVIDER LOOP FILTER XFC PAD ÷2 SLDV <5:0> EXTALi SYN <5:0> ×2 PLLCLK XCLK Figure 12-2.
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Freescale Semiconductor, Inc. Clock Functions Acquisition and Tracking Modes 12.5 Acquisition and Tracking Modes The lock detector compares the frequencies of the VCO feedback clock, DIVCLK, and the final reference clock, REFCLK. Therefore, the speed of the lock detector is directly proportional to the final reference frequency. The circuit determines the mode of the PLL and the lock condition based on this comparison. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clock Functions for the base clock. See Clock Divider Chains. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. Freescale Semiconductor, Inc... The following conditions apply when the PLL is in automatic bandwidth control mode: • The ACQ bit is a read-only indicator of the mode of the filter.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes 12.6 Limp-Home and Fast STOP Recovery modes If the crystal frequency is not available due to a crystal failure or a long crystal start-up time, the MCU system clock can be supplied by the VCO at its minimum operating frequency, f VCOMIN. This mode of operation is called Limp-Home Mode and is only available when the VDDPLL supply voltage is at VDD level (i.e.
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Freescale Semiconductor, Inc. Clock Functions VCO clock at its minimum frequency, f VCOMIN, is provided as the system clock, allowing the MCU to continue operating. Freescale Semiconductor, Inc... The MCU is said to be operating in “limp-home” mode with the forced VCO clock as the system clock. PLLON and BCSP (‘bus clock select PLL’) signals are forced high and the MCS (‘module clock select’) signal is forced low.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes values before the clock loss. All clocks return to their normal settings and Clock Monitor control is returned to the CME & FCME bits. If AUTO and BCSP bits were set before the clock loss (selecting the PLL to provide a system clock) the SYSCLK ramps-up and the PLL locks at the previously selected frequency.
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Freescale Semiconductor, Inc. Clock Functions 12.6.2 No Clock at Power-On Reset The voltage level on VDDPLL determines how the MCU responds to an external clock loss in this case. Freescale Semiconductor, Inc... With the VDDPLL supply voltage at VDD level, any reset sets the Clock Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit. Therefore, if the MCU is powered up without an external clock, limphome mode is entered provided the MCU is in a normal mode of operation.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes During this power up sequence, after the POR pulse falling edge, the VCO supplies the limp-home clock frequency to the 13-stage counter, as the BCSP output is forced high and MCS is forced low. XCLK, BCLK and MCLK are forced to be PCLK, which is supplied by the VCO at fVCOMIN. The initial period taken for the 13-stage counter to reach 4096 defines the internal reset period.
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Freescale Semiconductor, Inc. Clock Functions 12.6.3 STOP Exit and Fast STOP Recovery Stop mode is entered when a STOP instruction is executed. Recovery from STOP depends primarily on the state of the three status bits NOLHM, CME & DLY. Freescale Semiconductor, Inc... The DLY bit controls the duration of the waiting period between the actual exit for some key blocks (e.g. clock monitor, clock generators) and the effective exit from stop for all the rest of the MCU.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes 12.6.4 STOP exit without Limp Home mode, clock monitor disabled (NOLHM=1, CME=0, DLY=X) If Limp home mode is disabled (VDDPLL=VSS or NOLHM bit set) and the CME (or FCME) bit is cleared, the MCU goes into STOP mode when a STOP instruction is executed. If EXTALi clock is present then exit from STOP will occur normally using this clock.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Where the crystal start-up time is longer than the initial count of 4096 XCLK cycles, or in the absence of an external clock, the MCU recovers from STOP following the 4096 count in limp-home mode with both the LHOME flag set and the LHIF limp-home interrupt request set to indicate it is not operating at the desired frequency.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes Each time the 13-stage counter reaches a count of 4096 XCLK cycles (every 8192 cycles), a check of the clock monitor status is performed. If the clock monitor indicates the presence of an external clock limp-home mode is de-asserted, the LHOME flag is cleared and the limp-home interrupt flag is set.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions 12.6.9 Pseudo-STOP exit in Limp Home mode with Delay (NOLHM=0, CME=X, DLY=1) When coming out of Pseudo-STOP mode with the NOLHM bit cleared and the DLY bit set, the MCU goes into limp-home mode (regardless of the state of the CME or FCME bits). The VCO supplies the limp-home clock frequency to the 13-stage counter (XCLK). The BCSP output is forced high and MCS is forced low.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes 12.6.11 Pseudo-STOP exit without Limp Home mode, clock monitor enabled (NOLHM=1, CME=1, DLY=X) If the NOLHM bit is set and the CME (or FCME) bits are set, a clock monitor failure is detected when a STOP instruction is executed and the MCU resets via the clock monitor reset vector. 12.6.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions . . Table 12-1. Summary of STOP Mode Exit Conditions Mode Conditions Summary STOP exit without Limp Home mode, clock monitor disabled NOLHM=1 CME=0 DLY=X Oscillator must be stable within 4096 XCLK cycles. XCLK can be modified by SLOW divider register. Use of DLY=0 only recommended with external clock.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes 12.6.14 PLL Register Descriptions RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 0 0 0 0 0 0 0 0 SYNR — Synthesizer Register $0038 Read anytime, write anytime, except when BCSP = 1 (PLL selected as bus clock).
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Freescale Semiconductor, Inc. Clock Functions Bit 7 6 5 4 3 2 1 Bit 0 LOCKIF LOCK 0 0 0 0 LHIF LHOME 0 0 0 0 0 0 0 0 RESET: PLLFLG — PLL Flags $003B Read anytime, refer to each bit for write conditions. Freescale Semiconductor, Inc... LOCKIF — PLL Lock Interrupt Flag 0 = No change in LOCK bit. 1 = LOCK condition has changed, either from a locked state to an unlocked state or vice versa. To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home mode.
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Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes Bit 7 6 5 4 3 2 1 Bit 0 LOCKIE PLLON AUTO ACQ 0 PSTP LHIE NOLHM 0 —(1) 1 0 0 0 0 —(2) RESET: PLLCR — PLL Control Register $003C 1. Set when VDDPLL power supply is high. Forced to 0 when VDDPLL is low. 2. Cleared when VDDPLL power supply is high. Forced to 1 when VDDPLL is low. Freescale Semiconductor, Inc... Read and write anytime. Exceptions are listed below for each bit.
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Freescale Semiconductor, Inc. Clock Functions ACQ — Not in Acquisition If AUTO = 1 (ACQ is Read Only) 0 = PLL VCO is not within the desired tolerance of the target frequency. The loop filter is in high bandwidth, acquisition mode. 1 = After the phase lock loop circuit is turned on, indicates the PLL VCO is within the desired tolerance of the target frequency. The loop filter is in low bandwidth, tracking mode. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Clock Functions Limp-Home and Fast STOP Recovery modes RESET: Bit 7 6 5 4 3 2 1 Bit 0 0 BCSP BCSS 0 0 MCS 0 0 0 0 0 0 0 0 0 0 CLKSEL — Clock Generator Clock select Register $003D Read and write anytime. Exceptions are listed below for each bit. Freescale Semiconductor, Inc... BCSP and BCSS bits determine the clock used by the main system including the CPU and buses.
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Freescale Semiconductor, Inc. Clock Functions Bit 7 6 5 4 3 2 1 Bit 0 0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDV0 0 0 0 0 0 0 0 0 RESET: SLOW — Slow mode Divider Register $003E Read and write anytime. Freescale Semiconductor, Inc... A write to this register changes the SLWCLK frequency with minimum delay (less than one SLWCLK cycle), thus allowing immediate tuneup of the performance versus power consumption for the modules using this clock.
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Freescale Semiconductor, Inc. Clock Functions System Clock Frequency Formulae 12.7 System Clock Frequency Formulae See Figure 12-6: SLWCLK = EXTALi / ( 2 x SLOW ) SLOW = 1,2,..63 SLWCLK = EXTALi SLOW = 0 PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions 12.8 Clock Divider Chains Figure 12-6, Figure 12-7, Figure 12-8, and Figure 12-9 summarize the clock divider chains for the various peripherals on the MC68HC912DT128A.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Clock Divider Chains Bus clock select bits BCSP and BCSS in the clock select register (CLKSEL) determine which clock drives SYSCLK for the main system including the CPU and buses. BCSS has no effect if BCSP is set. During the transition, the clock select output will be held low and all CPU activity will cease until the transition is complete.
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Freescale Semiconductor, Inc. Clock Functions MCLK REGISTER: TMSK2 BITS: PR2, PR1, PR0 0:0:0 TEN REGISTER: MCCTL BITS: MCPR1, MCPR0 0:0 MCEN ÷2 0:0:1 ÷4 0:1 ÷2 0:1:0 ÷2 1:0 ÷2 0:1:1 ÷2 1:1 MODULUS DOWN COUNTER REGISTER: PACTL BITS: PAEN, CLK1, CLK0 0:x:x Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions In addition, windowed COP operation can be selected. In this mode, writes to the COPRST register must occur in the last 25% of the selected period. A premature write will also reset the part. 12.10 Real-Time Interrupt There is a real time (periodic) interrupt available to the user. This interrupt will occur at one of seven selected rates. An interrupt flag and an interrupt enable bit are associated with this function.
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Freescale Semiconductor, Inc. Clock Functions Clock Function Registers 12.12 Clock Function Registers All register addresses shown reflect the reset state. Registers may be mapped to any 2K byte space. RESET: Bit 7 6 5 4 3 2 1 Bit 0 RTIE RSWAI RSBCK Reserved RTBYP RTR2 RTR1 RTR0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... RTICTL — Real-Time Interrupt Control Register $0014 RTIE — Real Time Interrupt Enable Read and write anytime.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions RTR2, RTR1, RTR0 — Real-Time Interrupt Rate Select Read and write anytime. Rate select for real-time interrupt. The clock used for this module is the XCLK. Table 12-4. Real Time Interrupt Rates RTR2 RTR1 RTR0 Divide X By: Time-Out Period Time-Out Period Time-Out Period Time-Out Period X = 125 KHz X = 500 KHz X = 2.0 MHz X = 8.0 MHz OFF OFF OFF OFF 0 0 0 OFF 0 0 1 213 65.536 ms 16.384 ms 4.096 ms 1.024 ms 131.
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Freescale Semiconductor, Inc. Clock Functions Clock Function Registers Bit 7 6 5 4 3 2 1 Bit 0 CME FCME FCMCOP WCOP DISR CR2 CR1 CR0 RESET: 0/1 0 0 0 0 1 1 1 Normal RESET: 0/1 0 0 0 1 1 1 1 Special COPCTL — COP Control Register $0016 CME — Clock Monitor Enable Read and write anytime. Freescale Semiconductor, Inc... If FCME is set, this bit has no meaning nor effect. 0 = Clock monitor is disabled. Slow clocks and stop instruction may be used.
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Freescale Semiconductor, Inc. Clock Functions FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset Writes are not allowed in normal modes, anytime in special modes. Read anytime. Freescale Semiconductor, Inc... If DISR is set, this bit has no effect. 0 = Normal operation. 1 = A clock monitor failure reset or a COP failure reset is forced depending on the state of CME and if COP is enabled. CME COP enabled Forced reset 0 0 none 0 1 COP failure 1 0 Clock monitor failure 1 1 Both(1) 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Clock Functions Clock Function Registers Table 12-5. COP Watchdog Rates CR2 CR1 CR0 Window COP enabled: Divide XCLK by 8.0 MHz XCLK Time-out Window start (1) Window end Effective Window (2) 0 0 0 OFF OFF OFF OFF OFF 0 0 1 2 13 1.024 ms -0/+0.256 ms 0.768 ms 0.768 ms 0 % (3) 0 1 0 2 15 4.096 ms -0/+0.256 ms 3.072 ms 3.840 ms 18.8 % 0 1 1 2 17 16.384 ms -0/+0.256 ms 12.288 ms 16.128 ms 23.
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Freescale Semiconductor, Inc. Clock Functions Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 RESET: COPRST — Arm/Reset COP Timer Register $0017 Always reads $00. Freescale Semiconductor, Inc... Writing $55 to this address is the first step of the COP watchdog sequence. Writing $AA to this address is the second step of the COP watchdog sequence.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator Contents Technical Data — MC68HC912DT128A Section 13. Oscillator 13.1 Contents 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.3 MC68HC912DT128A Oscillator Specification . . . . . . . . . . . .194 13.4 MC68HC912Dx128C Colpitts Oscillator Specification . . . . . . 197 13.5 MC68HC912Dx128P Pierce Oscillator Specification . . . . . . . 212 13.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator mask set. This implementation, described in section 13.5 MC68HC912Dx128P Pierce Oscillator Specification, utilises the Automatic Level Control circuit to provide a lower power oscillator than traditional Pierce oscillators based on simple inverter circuits. In this section of the document, the term MC68HC912Dx128P refers only to the MC68HC912DT128P and MC68HC912DG128P devices.
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Freescale Semiconductor, Inc. Oscillator MC68HC912DT128A Oscillator Specification BUF - CFLT 2 OTA + RFLT - Freescale Semiconductor, Inc... ALC + BIAS EN RFLT CFLT GM RESD EXTAL XTAL CX-EX Resonator CX-VSS Figure 13-1. MC68HC912DT128A Colpitts Oscillator Architecture MC68HC912DT128A — Rev 4.0 MOTOROLA Technical Data Oscillator For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Oscillator 13.3.2 MC68HC912DT128A Oscillator Design Guidelines Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buffer. In addition to published errata for the MC68HC912DT128A, the following guidelines must be followed or failure in operation may occur.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128C Colpitts Oscillator Specification NOTE: EXTAL and XTAL routing resistances are less important than capacitances. Using minimum width traces is an acceptable trade-off to reduce capacitance. 13.4 MC68HC912Dx128C Colpitts Oscillator Specification This section applies to the 1L05H mask set, which refers to the newest set of CGM improvements (to the MC68HC912DT128A) with the Colpitts oscillator configuration enabled.
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Freescale Semiconductor, Inc. Oscillator BUF - CFLT 2 OTA + RFLT - Freescale Semiconductor, Inc... ALC + BIAS EN RFLT CFLT GM RESD EXTAL XTAL CX-EX Resonator CX-VSS Figure 13-2.
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Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128C Colpitts Oscillator Specification • The bias current to the amplifier was optimized for less variation over process. • The input ESD resistor from EXTAL to the gate of the oscillator amplifier was changed to provide a parallel path, reducing parasitic phase shift in the oscillator. 13.4.1.1 Clock Buffer Hysteresis Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator 13.4.1.2 Internal Parasitic Reduction Any oscillator circuit’s gain margin is reduced when a low AC-impedance (low resistance or high capacitance) is placed in parallel with the resonator. In the Colpitts oscillator configuration, this impedance is dominated by the parasitic capacitance from the EXTAL pin to VSS.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128C Colpitts Oscillator Specification 13.4.1.4 Input ESD Resistor Path Modification To satisfy the condition of oscillation, the oscillator circuit must not only provide the correct amount of gain but also the correct amount of phase shift. In the Colpitts configuration, the phase shift due to parasitics in the input path to the gate of the transconductance amplifier must be as low as possible.
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Freescale Semiconductor, Inc. Oscillator yield an unacceptable NRM for a worst-case situation (the slope of the NRM vs. capacitance curve is very steep, indicating severe sensitivity to small variations). If the NRM optimization happened to be performed on a best-case sample set, there could be unexpected sensitivity at worstcase. Negative Resistance Margin vs. Capacitance 100 Negative Resistance Margin Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128C Colpitts Oscillator Specification 13.4.2.2 Gain Margin The Gain Margin of the oscillator indicates the amount the gain of the oscillator can vary while maintaining oscillation.
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Freescale Semiconductor, Inc. Oscillator Similarly, if meeting a traditional NRM optimization criteria is important, then the components determined by this method are acceptable if the same components yield a maximum allowed ESR greater than the maximum ESR of the crystal while maintaining the worst case Gain Margin of 2. There is no guarantee that components chosen through traditional NRM optimization techniques will yield acceptable results across all expected variations. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128C Colpitts Oscillator Specification 13.4.3 Important Information For Calculating Component Values Before attempting to apply the information in section 13.4.2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator 6. If the frequency of the crystal falls between listed values, determine the appropriate component for the listed frequency values on either side and extrapolate. 7. The maximum allowed capacitor is the highest listed component, and the minimum allowed capacitor is the lowest listed component. ‘NA’ or ‘Not Allowed’ means the listed component is not valid or allowed for the given frequency, Shunt Capacitance, and VDDPLL setting. 13.4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128C Colpitts Oscillator Specification Table 13-1. MC68HC912Dx128C EXTAL–XTAL Capacitor Values vs. Maximum ESR, Shunt Capacitance, and VDDPLL setting Maximum ESR vs.
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Freescale Semiconductor, Inc. Oscillator Maximum ESR vs. EXTAL–XTAL capacitor value, 8MHz resonators Shunt Capacitance (pF) (VDDPLL=VDD) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128C Colpitts Oscillator Specification 13.4.4 MC68HC912Dx128C DC Blocking Capacitor Guidelines Due to the placement of the resonator from EXTAL to VSS and the nature of the microcontroller’s inputs, there will be a DC bias voltage of approximately (VDD–2V) across the pins of the resonator. For some resonators, this can have long-term reliability issues.
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Freescale Semiconductor, Inc. Oscillator BUF - CFLT 2 OTA + RFLT - Freescale Semiconductor, Inc... ALC + BIAS EN RFLT CFLT GM RESD EXTAL XTAL CX-EX 1nF DC-blocking capacitor Resonator CX-VSS CDC Figure 13-3. MC68HC912Dx128C Crystal with DC Blocking Capacitor Technical Data 210 MC68HC912DT128A — Rev 4.0 Oscillator For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128C Colpitts Oscillator Specification 13.4.5 MC68HC912Dx128C Oscillator Design Guidelines Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buffer.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator • NOTE: Minimize XTAL and EXTAL routing lengths to reduce EMC issues. EXTAL and XTAL routing resistances are less important than capacitances. Using minimum width traces is an acceptable trade-off to reduce capacitance. 13.
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Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128P Pierce Oscillator Specification BUF - CFLT 2 OTA + RFLT - Freescale Semiconductor, Inc... ALC + BIAS RFEEDBACK EN GM RESD EXTAL XTAL Resonator CEX-VSS CX-VSS Figure 13-4. MC68HC912Dx128P Pierce Oscillator Architecture There are the following primary differences between the previous Colpitts (‘A’) and new Pierce (‘P’) oscillator configurations: • Oscillator architecture was changed from Colpitts to Pierce.
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Freescale Semiconductor, Inc. Oscillator • The input ESD resistor from EXTAL to the gate of the oscillator amplifier was changed to provide a parallel path, reducing parasitic phase shift in the oscillator. 13.5.1.1 Oscillator Architecture Change from Colpitts to Pierce Freescale Semiconductor, Inc... The primary difference from the ‘A’ to the ‘P’ versions of the MC68HC912Dx128 is the architecture, or configuration, of the oscillator.
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Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128P Pierce Oscillator Specification lower amplitude for the Pierce. The amplitude will still be sufficient for robust operation across process, temperature, and voltage variance. 13.5.1.2 Clock Buffer Hysteresis Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator 13.5.1.3 Bias Current Process Optimization For proper oscillation, the gain margin of the oscillator must exceed one or the circuit will not oscillate. Process variance in the bias current (which controls the gain of the amplifier) can cause the gain margin to be much lower than typical. This can be as a result of either too much or too little current.
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Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128P Pierce Oscillator Specification 13.5.2 MC68HC912Dx128P Oscillator Circuit Specifications 13.5.2.1 Negative Resistance Margin Freescale Semiconductor, Inc... Negative Resistance Margin (NRM) is a figure of merit commonly used to qualify an oscillator circuit with a given resonator. NRM is an indicator of how much additional resistance in series with the resonator is tolerable while still maintaining oscillation.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator NRM measurement techniques can also generate misleading results when applied to Automatic Level Control (ALC) style oscillator circuits such as the D60x/Dx128x. Many NRM methods slowly increase series resistance until oscillation stops.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128P Pierce Oscillator Specification 13.5.2.3 Optimizing Component Values The maximum ESR possible (given a worst-case Gain Margin of 2) is not the optimum operating point. In some cases, the frequency accuracy of the oscillator is important and in other cases satisfying the traditional NRM measurement technique is important.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator • VDDPLL Setting — The Voltage applied to the VDDPLL pin (Logic 1 means VDDPLL is tied to the same potential as VDD). • Resonator Frequency — The frequency of oscillation of the resonator. • Maximum ESR — The maximum effective series resistance (ESR) of the resonator. This figure must include any increases due to ageing, power dissipation, temperature, process variation or particle contamination. 13.5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128P Pierce Oscillator Specification variation or particle contamination). 3. Within this range, choose the EXTAL–VSS capacitance closest to (CEXTAL–VSS = 2*CL – 10pF). 4. If the ideal component is between two valid component values (the maximum ESR is sufficient for both component values), then choose the component with the highest maximum ESR or choose an available component between the two listed values. 5.
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Freescale Semiconductor, Inc. Oscillator Table 13-2. MC68HC912Dx128P EXTAL–VSS, XTAL–VSS Capacitor Values vs. Maximum ESR, Shunt Capacitance, and VDDPLL setting Maximum ESR vs.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Oscillator MC68HC912Dx128P Pierce Oscillator Specification Maximum ESR vs.
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Freescale Semiconductor, Inc. Oscillator 13.5.4 MC68HC912Dx128P Guidelines Freescale Semiconductor, Inc... Proper and robust operation of the oscillator circuit requires excellent board layout design practice. Poor layout of the application board can contribute to EMC susceptibility, noise generation, slow starting oscillators, and reaction to noise on the clock input buffer.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 14. Pulse Width Modulator 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 14.3 PWM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . .229 14.4 PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240 14.
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Freescale Semiconductor, Inc. Pulse Width Modulator possible to know where the count is with respect to the duty value and software can be used to make adjustments by turning the enable bit off and on. The four PWM channel outputs share general-purpose port P pins. Enabling PWM pins takes precedence over the general-purpose port. When PWM are not in use, the port pins may be used for discrete input/output. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator Introduction CLOCK SOURCE (ECLK or Scaled ECLK) CENTR = 1 FROM PORT P DATA REGISTER RESET PWCNTx GATE (CLOCK EDGE SYNC) UP/DOWN (DUTY CYCLE) 8-BIT COMPARE = PWDTYx T Q (PERIOD) MUX MUX Q TO PIN DRIVER 8-BIT COMPARE = PWPERx PPOLx PWENx SYNC PPOL = 1 PPOL = 0 PWDTY (PWPER − PWDTY) × 2 PWPER × 2 PWDTY Figure 14-2. Block Diagram of PWM Center-Aligned Output Channel MC68HC912DT128A — Rev 4.
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Freescale Semiconductor, Inc. Pulse Width Modulator PSBCK PSBCK IS BIT 0 OF PWCTL REGISTER. INTERNAL SIGNAL LIMBDM IS ONE IF THE MCU IS IN BACKGROUND DEBUG MODE. LIMBDM CLOCK A MUX ECLK 0:0:0 8-BIT DOWN COUNTER 0:1:0 ÷2 ÷2 0:0:1 PWSCNT0 0:1:0 PCLK0 MUX 0:0:1 =0 CLOCK S0* 0:0:0 Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator PWM Register Descriptions 14.3 PWM Register Descriptions PWCLK — PWM Clocks and Concatenate RESET: $0040 Bit 7 6 5 4 3 2 1 Bit 0 CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0 0 0 0 0 0 0 0 0 Read and write anytime. CON23 — Concatenate PWM Channels 2 and 3 Freescale Semiconductor, Inc... When concatenated, channel 2 becomes the high-order byte and channel 3 becomes the low-order byte.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator Table 14-1. Clock A and Clock B Prescaler PCKA2 (PCKB2) 0 0 0 0 1 1 1 1 PCKA1 (PCKB1) 0 0 1 1 0 0 1 1 PCKA0 (PCKB0) 0 1 0 1 0 1 0 1 Value of Clock A (B) P P÷2 P÷4 P÷8 P ÷ 16 P ÷ 32 P ÷ 64 P ÷ 128 PWPOL — PWM Clock Select and Polarity $0041 Bit 7 6 5 4 3 2 1 Bit 0 PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0 0 0 0 0 0 0 0 0 RESET: Read and write anytime.
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Freescale Semiconductor, Inc. Pulse Width Modulator PWM Register Descriptions PPOL3 — PWM Channel 3 Polarity 0 = Channel 3 output is low at the beginning of the period; high when the duty count is reached. 1 = Channel 3 output is high at the beginning of the period; low when the duty count is reached. Freescale Semiconductor, Inc... PPOL2 — PWM Channel 2 Polarity 0 = Channel 2 output is low at the beginning of the period; high when the duty count is reached.
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Freescale Semiconductor, Inc. Pulse Width Modulator PWEN — PWM Enable $0042 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 PWEN3 PWEN2 PWEN1 PWEN0 0 0 0 0 0 0 0 0 RESET: Freescale Semiconductor, Inc... Setting any of the PWENx bits causes the associated port P line to become an output regardless of the state of the associated data direction register (DDRP) bit. This does not change the state of the data direction bit. When PWENx returns to zero, the data direction bit controls I/O direction.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator PWM Register Descriptions PWPRES — PWM Prescale Counter RESET: $0043 Bit 7 6 5 4 3 2 1 Bit 0 0 Bit 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 PWPRES is a free-running 7-bit counter. Read anytime. Write only in special mode (SMOD = 1). PWSCAL0 — PWM Scale Register 0 RESET: $0044 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Read and write anytime.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator PWSCAL1 — PWM Scale Register 1 $0046 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 RESET: Read and write anytime. A write will cause the scaler counter PWSCNT1 to load the PWSCAL1 value unless in special mode with DISCAL = 1 in the PWTST register. PWM channels 2 and 3 can select clock S1 (scaled) as its input clock by setting the control bit PCLK2 and PCLK3 respectively.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator PWM Register Descriptions The PWM counters are not reset when PWM channels are disabled. The counters must be reset prior to a new enable. Each counter may be read any time without affecting the count or the operation of the corresponding PWM channel. Writes to a counter cause the counter to be reset to $00 and force an immediate load of both duty and period registers with new values.
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Freescale Semiconductor, Inc. Pulse Width Modulator and then write the counter forcing a new period to start with the new period value. Period = Channel-Clock-Period × (PWPER + 1) Period = Channel-Clock-Period × (2 × PWPER) (CENTR = 0) (CENTR = 1) Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Pulse Width Modulator PWM Register Descriptions PWCTL — PWM Control Register RESET: $0054 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 PSWAI CENTR RDPP PUPP PSBCK 0 0 0 0 0 0 0 0 Read and write anytime. Freescale Semiconductor, Inc... PSWAI — PWM Halts while in Wait Mode 0 = Allows PWM main clock generator to continue while in wait mode. 1 = Halt PWM main clock generator when the part is in wait mode.
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Freescale Semiconductor, Inc. Pulse Width Modulator PWTST — PWM Special Mode Register (“Test”) $0055 Bit 7 6 5 4 3 2 1 Bit 0 DISCR DISCP DISCAL 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET: Read anytime but write only in special mode (SMODN = 0). These bits are available only in special mode and are reset in normal mode. Freescale Semiconductor, Inc... DISCR — Disable Reset of Channel Counter on Write to Channel Counter 0 = Normal operation.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Pulse Width Modulator PWM Register Descriptions PORTP — Port P Data Register $0056 Bit 7 6 5 4 3 2 1 Bit 0 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PWM – – – – PWM3 PWM2 PWM1 PWM0 RESET: – – – – – – – – PORTP can be read anytime. PWM functions share port P pins 3 to 0 and take precedence over the general-purpose port when enabled. When configured as input, a read will return the pin level.
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Freescale Semiconductor, Inc. Pulse Width Modulator 14.4 PWM Boundary Cases The boundary conditions for the PWM channel duty registers and the PWM channel period registers cause these results: Table 14-2. PWM Left-Aligned Boundary Conditions Freescale Semiconductor, Inc... PWDTYx $FF $FF ≥PWPERx ≥PWPERx – – PWPERx >$00 >$00 – – $00 $00 PPOLx 1 0 1 0 1 0 Output Low High High Low High Low Table 14-3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 15. Enhanced Capture Timer 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 15.3 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . 247 15.4 Timer Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 251 15.5 Timer and Modulus Counter Operation in Different Modes . . 275 15.
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Freescale Semiconductor, Inc. Enhanced Capture Timer This design specification describes the standard timer as well as the additional features. The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. Freescale Semiconductor, Inc...
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Enhanced Capture Timer Introduction ÷ 1, 2, ...
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Freescale Semiconductor, Inc. Enhanced Capture Timer ÷1, 2, ..., 128 M clock 16-bit Free-running 16 BIT MAIN mainTIMER timer Prescaler 16-bit load register ÷ 1, 4, 8, 16 M clock 16-bit modulus down counter Prescaler 0 RESET Comparator Pin logic Delay counter EDG0 TC0 capture/compare register TC0H hold register PAC0 LATCH0 PT0 PA0H hold register 0 RESET PT1 Pin logic Delay counter EDG1 TC1 capture/compare register TC1H hold register PAC1 LATCH1 Freescale Semiconductor, Inc...
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Enhanced Capture Timer Introduction Load holding register and reset pulse accumulator 0 EDG0 PT0 Edge detector 8-bit PAC0 (PACN0) Delay counter PA0H holding register Interrupt 0 EDG1 PT1 Edge detector 8-bit PAC1 (PACN1) Delay counter Host CPU data bus Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Enhanced Capture Timer To TCNT Counter CLK1 CLK0 Clock select (PAMOD) Edge detector PT7 PACLK PACLK / 256 PACLK / 65536 Freescale Semiconductor, Inc... Prescaled MCLK (TMSK2 bits PR2-PR0) 4:1 MUX Interrupt 8-bit PAC3 (PACN3) 8-bit PAC2 (PACN2) MUX PACA M clock Intermodule Bus Divide by 64 Interrupt 8-bit PAC1 (PACN1) 8-bit PAC0 (PACN0) Delay counter PACB Edge detector PT0 Figure 15-4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Enhanced Capture Timer Modes of Operation Pulse accumulator A PAD OC7 (OM7=1 or OL7=1) or (OC7M7 = 1) Figure 15-5. Block Diagram for Port7 with Output compare / Pulse Accumulator A 16-bit Main Timer PTn Delay counter Edge detector Set CnF Interrupt TCn Input Capture Reg. TCnH I.C. Holding Reg. BUFEN • LATQ • TFMOD Figure 15-6. C3F-C0F Interrupt Flag Setting 15.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Four IC channels are the same as on the standard timer with one capture register which memorizes the timer value captured by an action on the associated input pin. Four other IC channels, in addition to the capture register, have also one buffer called holding register. This permits to memorize two different timer values without generation of any interrupt.
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Freescale Semiconductor, Inc. Enhanced Capture Timer Enhanced Capture Timer Modes of Operation 15.3.1.2 Buffered IC Channels There are two modes of operations for the buffered IC channels. • IC Latch Mode: When enabled (LATQ=1), the main timer value is memorized in the IC register by a valid input pin transition. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer 15.3.2 Pulse Accumulators There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC buffered channels. A pulse accumulator counts the number of active edges at the input of its channel. The user can prevent 8-bit pulse accumulators counting further than $FF by PACMX control bit in ICSYS ($AB). In this case a value of $FF means that 255 counts or more have occurred.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions 15.4 Timer Register Descriptions Input/output pins default to general-purpose I/O lines until an internal function which uses that pin is specifically enabled. The timer overrides the state of the DDR to force the I/O state of each associated port line when an output compare using a port line is enabled. In these cases the data direction bits will have no affect on these lines.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer FOC[7:0] — Force Output Compare Action for Channel 7-0 A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “n” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCn register except the interrupt flag does not get set.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare action during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit.
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Freescale Semiconductor, Inc. Enhanced Capture Timer TSWAI — Timer Module Stops While in Wait 0 = Allows the timer module to continue running during wait. 1 = Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulators and modulus down counters. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer TCTL3 — Timer Control Register 3 $008A Bit 7 6 5 4 3 2 1 Bit 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A 0 0 0 0 0 0 0 0 RESET: TCTL4 — Timer Control Register 4 $008B Bit 7 6 5 4 3 2 1 Bit 0 EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A 0 0 0 0 0 0 0 0 RESET: Read or write anytime.
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Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions TMSK2 — Timer Interrupt Mask 2 RESET: $008D Bit 7 6 5 4 3 2 1 Bit 0 TOI 0 PUPT RDPT TCRE PR2 PR1 PR0 0 0 0 0 0 0 0 0 Read or write anytime. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Table 15-3. Prescaler Selection PR2 0 0 0 0 1 1 1 1 PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Prescale Factor 1 2 4 8 16 32 64 128 The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions TFLG2 — Main Timer Interrupt Flag 2 RESET: $008F Bit 7 6 5 4 3 2 1 Bit 0 TOF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, set the bit to one. Read anytime. Write used in clearing mechanism (set bits cause corresponding bits to be cleared).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions Freescale Semiconductor, Inc... PAEN — Pulse Accumulator A System Enable 0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable bits in ICPACR ($A8) are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled. 1 = Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse accumulator.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer CLK1, CLK0 — Clock Select Bits CLK1 CLK0 0 0 Use timer prescaler clock as timer counter clock Clock Source 0 1 Use PACLK as input to timer counter clock 1 0 Use PACLK/256 as timer counter clock frequency 1 1 Use PACLK/65536 as timer counter clock frequency If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions PAIF — Pulse Accumulator Input edge Flag Set when the selected edge is detected at the PT7 input pin. In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF. This bit is cleared by a write to the PAFLG register with bit 0 set.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1 in PBCTL, $B0) the PACN1 and PACN0 registers contents are respectively the high and low byte of the PACB. When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in PBFLG ($B1) is set. Full count register access should take place in one clock cycle.
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Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions ICLAT — Input Capture Force Latch Action When input capture latch mode is enabled (LATQ and BUFEN bit in ICSYS ($AB) are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3 and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse accumulators will be automatically cleared when the latch action occurs.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer MCFLG — 16-Bit Modulus Down-Counter FLAG Register $00A7 BIT 7 6 5 4 3 2 1 BIT 0 MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0 0 0 0 0 0 0 0 0 RESET: Read: any time Write: Only for clearing bit 7 MCZF — Modulus Counter Underflow Interrupt Flag The flag is set when the modulus down-counter reaches $0000. A write one to this bit clears the flag. Write zero has no effect.
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Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable 0 = 8-Bit Pulse Accumulator is disabled. 1 = 8-Bit Pulse Accumulator is enabled. DLYCT — Delay Counter Control Register BIT 7 6 5 4 3 2 1 BIT 0 0 0 0 0 0 0 DLY1 DLY0 0 0 0 0 0 0 0 0 Freescale Semiconductor, Inc... RESET: $00A9 Read or write any time.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer An IC register is empty when it has been read or latched into the holding register. A holding register is empty when it has been read. NOVWx — No Input Capture Overwrite 0 = The contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs. 1 = The related capture register or holding register cannot be written by an event unless they are empty (see IC Channels).
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Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions the main timer contents. At the next event the TCn data is transferred to the TCnH register, The TCn is updated and the CnF interrupt flag is set. See Figure 15-6. Freescale Semiconductor, Inc... In all other input capture cases the interrupt flag is set by a valid external event on PTn. 0 = The timer flags C3F–C0F in TFLG1 ($8E) are set when a valid input capture transition on the corresponding port pin occurs.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer 0 = Queue Mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value. 1 = Latch Mode is enabled.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions Write: data stored in an internal latch (drives pins only if configured for output) Since the Output Compare 7 shares the pin with Pulse Accumulator input, the only way for Pulse accumulator to receive an independent input from Output Compare 7 is setting both OM7 & OL7 to be zero, and also OC7M7 in OC7M register to be zero.
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Freescale Semiconductor, Inc. Enhanced Capture Timer PBCTL — 16-Bit Pulse Accumulator B Control Register $00B0 BIT 7 6 5 4 3 2 1 BIT 0 0 PBEN 0 0 0 0 PBOVI 0 0 0 0 0 0 0 0 0 RESET: Read or write any time. Freescale Semiconductor, Inc... 16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit pulse accumulators PAC1 and PAC0. When PBEN is set, the PACB is enabled. The PACB shares the input pin with IC0.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer Timer Register Descriptions PBOVF — Pulse Accumulator B Overflow Flag This bit is set when the 16-bit pulse accumulator B overflows from $FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from $FF to $00. This bit is cleared by a write to the PBFLG register with bit 1 set. Any access to the PACN1 and PACN0 registers will clear the PBOVF flag in this register when TFFCA bit in register TSCR($86) is set.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Enhanced Capture Timer bit is set, reads of the MCCNT will return the contents of the load register. If a $0000 is written into MCCNT and modulus counter while LATQ and BUFEN in ICSYS ($AB) register are set, the input capture and pulse accumulator registers will be latched. With a $0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag in MCFLG register.
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Freescale Semiconductor, Inc. Enhanced Capture Timer Timer and Modulus Counter Operation in Different Modes Read: any time Write: has no effect. These registers are used to latch the value of the input capture registers TC0 – TC3. The corresponding IOSx bits in TIOS ($80) should be cleared (see IC Channels). Freescale Semiconductor, Inc... 15.5 Timer and Modulus Counter Operation in Different Modes STOP: Timer and modulus counter are off since clocks are stopped.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Enhanced Capture Timer Technical Data 276 MC68HC912DT128A — Rev 4.0 Enhanced Capture Timer For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 16. Multiple Serial Interface 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 16.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 16.4 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . .278 16.5 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . .
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Multiple Serial Interface 16.3 Block diagram SCI0 SCI1 RxD0 PS0 TxD0 PS1 RxD1 TxD1 MISO/SISO SPI MOSI/MOMI DDRS/IOCTLR MSI PORT S I/O DRIVERS Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. PS2 PS3 PS4 PS5 SCK PS6 CS/SS PS7 HC12A4 MSI BLOCK Figure 16-1. Multiple Serial Interface Block Diagram 16.4 Serial Communication Interface (SCI) Two serial communication interfaces are available on the MC68HC912DT128A.
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Multiple Serial Interface Serial Communication Interface (SCI) MCLK BAUD RATE CLOCK SCI TRANSMITTER MSB DIVIDER Rx Baud Rate PARITY GENERATOR LSB 10-11 Bit SHIFT REG TxD BUFFER/SCxDRL SCxBD/SELECT PIN CONTROL / DDRS / PORT S Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface 16.4.1 Data Format The serial data format requires the following conditions: • An idle-line in the high state before transmission or reception of a message. • A start bit (logic zero), transmitted or received, that indicates the start of each character. • Data that is transmitted or received least significant bit (LSB) first. • A stop bit (logic one), used to indicate the end of a frame.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface Serial Communication Interface (SCI) 16.4.3 SCI Register Descriptions Control and data registers for the SCI subsystem are described below. The memory address indicated for each register is the default address that is in use after reset. Both SCI have identical control registers mapped in two blocks of eight bytes.
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Freescale Semiconductor, Inc. Multiple Serial Interface SC0CR1/SC1CR1 — SCI Control Register 1 RESET: Bit 7 LOOPS 0 6 WOMS 0 5 RSRC 0 $00C2/$00CA 4 M 0 3 WAKE 0 2 ILT 0 1 PE 0 Bit 0 PT 0 Read or write anytime. Freescale Semiconductor, Inc... LOOPS — SCI LOOP Mode/Single Wire Mode Enable 0 = SCI transmit and receive sections operate normally. 1 = SCI receive section is disconnected from the RXD pin and the RXD pin is available as general purpose I/O.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface Serial Communication Interface (SCI) RSRC — Receiver Source When LOOPS = 1, the RSRC bit determines the internal feedback path for the receiver. 0 = Receiver input is connected to the transmitter internally (not TXD pin) 1 = Receiver input is connected to the TXD pin Table 16-2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface In the long mode, the SCI circuitry does not begin counting ones in the search for the idle line condition until a stop bit is received. Therefore, the last byte’s stop bit and preceding “1” bits do not affect how quickly an idle line condition can be detected. PE — Parity Enable 0 = Parity is disabled. 1 = Parity is enabled.
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Freescale Semiconductor, Inc. Multiple Serial Interface Serial Communication Interface (SCI) RIE — Receiver Interrupt Enable 0 = RDRF and OR interrupts disabled, RAF interrupt in WAIT mode disabled 1 = SCI interrupt will be requested whenever the RDRF or OR status flag is set, or when RAF is set while in WAIT mode with VDDPLL high. Freescale Semiconductor, Inc... ILIE — Idle Line Interrupt Enable 0 = IDLE interrupts disabled 1 = SCI interrupt will be requested whenever the IDLE status flag is set.
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Freescale Semiconductor, Inc. Multiple Serial Interface SC0SR1/SC1SR1 — SCI Status Register 1 RESET: Bit 7 TDRE 1 6 TC 1 5 RDRF 0 $00C4/$00CC 4 IDLE 0 3 OR 0 2 NF 0 1 FE 0 Bit 0 PF 0 Freescale Semiconductor, Inc... The bits in these registers are set by various conditions in the SCI hardware and are automatically cleared by special acknowledge sequences.
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Freescale Semiconductor, Inc. Multiple Serial Interface Serial Communication Interface (SCI) RDRF — Receive Data Register Full Flag Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. RDRF is set if a received character is ready to be read from SCxDR. Clear the RDRF flag by reading SCxSR1 with RDRF set and then reading SCxDR. 0 = SCxDR empty 1 = SCxDR full IDLE — Idle Line Detected Flag Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface PF — Parity Error Flag Indicates if received data’s parity matches parity bit. This feature is active only when parity is enabled. The type of parity tested for is determined by the PT (parity type) bit in SCxCR1. 0 = Parity correct 1 = Incorrect parity detected SC0SR2/SC1SR2 — SCI Status Register 2 RESET: Bit 7 0 0 6 0 0 5 0 0 $00C5/$00CD 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 RAF 0 Read anytime.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface Serial Peripheral Interface (SPI) R8 — Receive Bit 8 Read anytime. Write has no meaning or affect. This bit is the ninth serial data bit received when the SCI system is configured for nine-data-bit operation. T8 — Transmit Bit 8 Read or write anytime. This bit is the ninth serial data bit transmitted when the SCI system is configured for nine-data-bit operation.
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Freescale Semiconductor, Inc. Multiple Serial Interface 16.5.1 SPI Baud Rate Generation The E Clock is input to a divider series and the resulting SPI clock rate may be selected to be E divided by 2, 4, 8, 16, 32, 64, 128 or 256. Three bits in the SP0BR register control the SPI clock rate. This baud rate generator is activated only when SPI is in the master mode and serial transfer is taking place. Otherwise this divider is disabled to save power. Freescale Semiconductor, Inc... 16.5.
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Multiple Serial Interface Serial Peripheral Interface (SPI) MCU P CLOCK (SAME AS E RATE) DIVIDER ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256 8-BIT SHIFT REGISTER S M MISO PS4 M S MOSI PS5 READ DATA BUFFER SP0DR SPI DATA REGISTER SELECT LSBF PIN CONTROL LOGIC SPR0 SPR1 SPR2 SHIFT CONTROL LOGIC CLOCK SCK PS6 S CLOCK LOGIC SP0BR SPI BAUD RATE REGISTER M SS PS7 MSTR SPE SPI CONTROL SPI INTERRUPT REQUEST SP0SR SPI STATUS REGISTER SP0CR1 SPI CONTROL REGISTER 1 SPC0 RDS PUPS LSBF SSOE CPHA CPOL
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Freescale Semiconductor, Inc. Multiple Serial Interface Begin Transfer End SCK (CPOL=0) SCK (CPOL=1) If next transfer begins here SAMPLE I (MOSI/MISO) Freescale Semiconductor, Inc... CHANGE O (MOSI pin) CHANGE O (MISO pin) SEL SS (O) (Master only) SEL SS (I) MSB first (LSBF=0): LSB first (LSBF=1): tL MSB LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB tI tT tL Minimum 1/2 SCK for tT, tl, tL HC12 SPI CLOCK FORM 0 Figure 16-4.
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Multiple Serial Interface Serial Peripheral Interface (SPI) Transfer Begin End SCK (CPOL=0) SCK (CPOL=1) SAMPLE I (MOSI/MISO) If next transfer begins here Freescale Semiconductor, Inc... Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface 16.5.4 Bidirectional Mode (MOMI or SISO) In bidirectional mode, the SPI uses only one serial data pin for external device interface. The MSTR bit decides which pin to be used. The MOSI pin becomes serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The direction of each serial I/O pin depends on the corresponding DDRS bit. Figure 16-6.
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Freescale Semiconductor, Inc. Multiple Serial Interface Serial Peripheral Interface (SPI) 1 = Hardware interrupt sequence is requested each time the SPIF or MODF status flag is set SPE — SPI System Enable 0 = SPI internal hardware is initialized and SPI system is in a lowpower disabled state. 1 = PS[4:7] are dedicated to the SPI function When MODF is set, SPE always reads zero. SP0CR1 must be written as part of a mode fault recovery sequence. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Multiple Serial Interface SP0CR2 — SPI Control Register 2 RESET: Bit 7 0 0 6 0 0 $00D1 5 0 0 4 0 0 3 PUPS 1 2 RDPS 0 1 SSWAI 0 Bit 0 SPC0 0 Read or write anytime. Freescale Semiconductor, Inc... PUPS — Pull-Up Port S Enable 0 = No internal pull-ups on port S 1 = All port S input pins have an active pull-up device.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface Serial Peripheral Interface (SPI) SP0BR — SPI Baud Rate Register RESET: Bit 7 0 0 6 0 0 $00D2 5 0 0 4 0 0 3 0 0 2 SPR2 0 1 SPR1 0 Bit 0 SPR0 0 Read anytime. Write anytime. At reset, E Clock divided by 2 is selected. SPR[2:0] — SPI Clock (SCK) Rate Select Bits These bits are used to specify the SPI clock rate. Table 16-4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface WCOL — Write Collision Status Flag The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. Automatically cleared by a read of the SP0SR (with WCOL set) followed by an access (read or write) to the SP0DR register.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Multiple Serial Interface Port S some slave devices are very simple and either accept data from the master without returning data to the master or pass data to the master without requiring data from the master. 16.6 Port S In all modes, port S bits PS[7:0] can be used for either general-purpose I/O, or with the SCI and SPI subsystems. During reset, port S pins are configured as high-impedance inputs (DDRS is cleared).
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Freescale Semiconductor, Inc. Multiple Serial Interface DDS2, DDS0 — Data Direction for Port S Bit 2 and Bit 0 If the SCI receiver is configured for two-wire SCI operation, corresponding port S pins will be input regardless of the state of these bits. DDS3, DDS1 — Data Direction for Port S Bit 3 and Bit 1 Freescale Semiconductor, Inc... If the SCI transmitter is configured for two-wire SCI operation, corresponding port S pins will be output regardless of the state of these bits.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 17. Inter IC Bus 17.1 Contents 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 17.3 IIC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 17.4 IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 17.5 IIC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Inter IC Bus 17.3 IIC Features Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Inter IC Bus IIC Features ADDR & CONTROL DATA INTERRUPT Freescale Semiconductor, Inc... ADDR_DECODE CTRL_REG DATA_MUX FREQ_REG ADDR_REG STATUS_REG DATA_REG In/Out Input Data Sync Shift Start, Register Stop & Arbitration Control Clock Control Address Compare SCL SDA Figure 17-1. IIC Block Diagram MC68HC912DT128A — Rev 4.0 MOTOROLA Technical Data Inter IC Bus For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc. Inter IC Bus 17.4 IIC System Configuration The IIC system uses a Serial Data line (SDA) and a Serial Clock Line (SCL) for data transfer. All devices connected to it must have open drain or open collector outputs. Logic “and” function is exercised on both lines with external pull-up resistors, the value of these resistors is system dependent. Freescale Semiconductor, Inc... 17.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus IIC Protocol 17.5.1 START Signal When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical high), a master may initiate communication by sending a START signal. As shown in Figure 17-2, a START signal is defined as a high-to-low transition of SDA while SCL is high.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 17-2. There is one clock pulse on SCL for each data bit, the MSB being transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine clock pulses.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus IIC Protocol 17.5.6 Arbitration Procedure IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus Start Counting High Period WAIT SCL1 SCL2 SCL Internal Counter Reset Figure 17-3. IIC Clock Synchronization 17.5.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces the master clock into wait states until the slave releases the SCL line. 17.5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus IIC Register Descriptions 17.6 IIC Register Descriptions .
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Freescale Semiconductor, Inc. Inter IC Bus Freescale Semiconductor, Inc... Table 17-1.
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Freescale Semiconductor, Inc. Inter IC Bus IIC Register Descriptions Freescale Semiconductor, Inc... Table 17-2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus Table 17-2.
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Freescale Semiconductor, Inc. Inter IC Bus IIC Register Descriptions IBIE — IIC Bus Interrupt Enable 0 = Interrupts from the IIC module are disabled. Note that this does not clear any currently pending interrupt condition. 1 = Interrupts from the IIC module are enabled. An IIC interrupt occurs provided the IBIF bit in the status register is also set. MS/SL — Master/Slave mode select bit Freescale Semiconductor, Inc... Upon reset, this bit is cleared.
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Freescale Semiconductor, Inc. Inter IC Bus RSTA — Repeat Start Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 = Generate repeat start cycle Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus IIC Register Descriptions NOTE: If, after trying to generate a START signal and neither the IBB nor IBAL bits are set after several cycles, the IIC should be disabled and reenabled with IBEN bit. IBAL — Arbitration Lost The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost. Arbitration is lost in the following circumstances: 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus IBIF — IIC Bus Interrupt Flag The IBIF bit is set when an interrupt is pending, which will cause a processor interrupt request provided IBIE is set. IBIF is set when one of the following events occurs: 1. Complete one byte transfer (set at the falling edge of the 9th clock). 2. Receive a calling address that matches its own specific address in slave receive mode. 3. Arbitration lost.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus IIC Register Descriptions IBPURD — Pull-Up and Reduced Drive for Port IB RESET: Bit 7 0 0 6 0 0 5 0 0 $00E5 4 RDPIB 0 3 0 0 2 0 0 1 0 0 Bit 0 PUPIB 0 Read and write anytime RDPIB - Reduced Drive of Port IB 0 = All port IB output pins have full drive enabled. 1 = All port IB output pins have reduced drive capability. PUPIB - Pull-Up Port IB Enable 0 = Port IB pull-ups are disabled.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus DDRIB — Data Direction for Port IB Register RESET: Bit 7 DDRIB7 0 6 DDRIB6 0 5 DDRIB5 0 $00E7 4 DDRIB4 0 3 DDRIB3 0 2 DDRIB2 0 1 DDRIB1 0 Bit 0 DDRIB0 0 Read and write anytime DDRIB[7:2]— Port IB [7:2] Data direction Each bit determines the primary direction for each pin configured as general-purpose I/O. 0 = Associated pin is a high-impedance input. 1 = Associated pin is an output.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus IIC Programming Examples 17.7.2 Generation of START After completion of the initialization procedure, serial data can be transmitted by selecting the 'master transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC Bus Busy bit (IBB) must be tested to check whether the serial bus is free. If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus monitor the IBIF bit rather than the TCF bit since their operation is different when arbitration is lost. Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR, then the Tx/Rx bit should be toggled at this stage.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus IIC Programming Examples be done by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master receiver.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Inter IC Bus receive mode. The slave will drive SCL low in-between byte transfers, SCL is released when the IBDR is accessed in the required mode. In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must be switched from transmitter mode to receiver mode by software.
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Freescale Semiconductor, Inc. Inter IC Bus Clear IBIF Master Mode ? Y Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Inter IC Bus Technical Data 324 MC68HC912DT128A — Rev 4.0 Inter IC Bus For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 18. MSCAN Controller 18.1 Contents 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 18.3 External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 18.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 18.5 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller The msCAN12 is the specific implementation of the Motorola scalable CAN (msCAN) concept targeted for the Motorola M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification dated September 1991.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Message Storage CAN station 1 CAN station 2 ..... CAN station n CAN system msCAN12 Controller TxCAN RxCAN Transceiver CAN Figure 18-1. The CAN System 18.4 Message Storage msCAN12 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 18.4.1 Background Modern application layer software is built upon two fundamental assumptions: 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Above behavior can not be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be completed within the inter-frame sequence (IFS) in order to be able to send an uninterrupted stream of messages.
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Freescale Semiconductor, Inc. MSCAN Controller Message Storage status of the foreground receive buffer. When the buffer contains a correctly received message with matching identifier this flag is set. Freescale Semiconductor, Inc... After the msCAN12 successfully received a message into the background buffer and if the message passes the filter, it copies the content of RxBG into RxFG(1), sets the RXF flag, and emits a receive interrupt to the CPU(2).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller msCAN12 CPU bus RxBG RxFG RXF Tx0 TXE PRIO Tx1 TXE PRIO Tx2 TXE PRIO Figure 18-2. User Model for Message Buffer Organization 18.4.3 Transmit Structures The msCAN12 has a triple transmit buffer scheme in order to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers are arranged as shown in Figure 18-2.
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Freescale Semiconductor, Inc. MSCAN Controller Message Storage called local priority field (PRIO) (see Transmit Buffer Priority Registers (TBPR)). In order to transmit a message, the CPU12 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the msCAN12 transmitter flag register (CTFLG) (see msCAN12 Transmitter Flag Register (CTFLG)). Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MSCAN Controller a transmit interrupt. The transmit interrupt handler software can tell from the setting of the ABTAK flag whether the message was actually aborted (ABTAK=1) or sent in the meantime (ABTAK=0). 18.5 Identifier Acceptance Filter Freescale Semiconductor, Inc... A very flexible programmable generic identifier acceptance filter has been introduced in order to reduce the CPU interrupt loading.
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Freescale Semiconductor, Inc. MSCAN Controller Identifier Acceptance Filter ID28 IDR0 Freescale Semiconductor, Inc... ID10 IDR0 ID21 ID20 IDR1 ID3 ID2 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR IDR1 IDE AM7 CIDMRO AM0 AM7 CIDMR1 AM0 AM7 CIDMR2 AM0 AM7 CIDMR3 AM0 AC7 CIDARO AC0 AC7 CIDAR1 AC0 AC7 CIDAR2 AC0 AC7 CIDAR3 AC0 ID accepted (Filter 0 hit) Figure 18-3.
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Freescale Semiconductor, Inc. MSCAN Controller ID28 IDR0 ID21 ID20 ID10 IDR0 ID3 ID2 IDR1 ID15 ID14 IDR2 ID7 ID6 IDR3 RTR IDR1 IDE AM7 CIDMRO AM0 AC7 CIDARO AC0 Freescale Semiconductor, Inc... ID accepted (Filter 0 hit) AM7 CIDMR1 AM0 AC7 CIDAR1 AC0 ID accepted (Filter 1 hit) AM7 CIDMR2 AM0 AC7 CIDAR2 AC0 ID accepted (Filter 2 hit) AM7 CIDMR3 AM0 AC7 CIDAR3 AC0 Figure 18-5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Interrupts three bits in the identifier acceptance control register (see msCAN12 Identifier Acceptance Control Register (CIDAC)). These identifier hit flags (IDHIT2–0) clearly identify the filter section that caused the acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. In case that more than one hit occurs (two or more filters match) the lower hit has priority.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller – Receiver error passive: the receive error counter has exceeded the error passive limit of 127 and msCAN12 has gone to error passive state. – Transmitter error passive: the transmit error counter has exceeded the error passive limit of 127 and msCAN12 has gone to error passive state. – Bus off: the transmit error counter has exceeded 255 and msCAN12 has gone to BUSOFF state. 18.6.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Protocol Violation Protection Table 18-1. msCAN12 Interrupt Vectors Function Wake-Up Error Interrupts Receive Transmit Source WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF TXE0 TXE1 TXE2 Local Mask WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE TXEIE0 TXEIE1 TXEIE2 Global Mask I Bit 18.
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Freescale Semiconductor, Inc. MSCAN Controller 18.8 Low Power Modes The msCAN12 has three modes with reduced power consumption compared to normal mode. In SLEEP and SOFT_RESET mode, power consumption is reduced by stopping all clocks except those to access the registers. In POWER_DOWN mode, all clocks are stopped and no power is consumed. Freescale Semiconductor, Inc... The WAI and STOP instructions put the MCU in low power consumption stand-by modes.
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Freescale Semiconductor, Inc. MSCAN Controller Low Power Modes 18.8.1 msCAN12 SLEEP Mode Freescale Semiconductor, Inc... The CPU can request the msCAN12 to enter this low-power mode by asserting the SLPRQ bit in the module configuration register (see Figure 18-6).
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Freescale Semiconductor, Inc. MSCAN Controller NOTE: The MCU cannot clear the SLPRQ bit before the msCAN12 is in SLEEP mode (SLPAK = 1). Freescale Semiconductor, Inc... After wake-up, the msCAN12 waits for 11 consecutive recessive bits to synchronize to the bus. As a consequence, if the msCAN12 is woken-up by a CAN frame, this frame will not be received. The receive message buffers (RxBG and RxFG) will contain messages if they were received before sleep mode was entered.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Low Power Modes 18.8.2 msCAN12 SOFT_RESET Mode In SOFT_RESET mode, the msCAN12 is stopped. Registers can still be accessed. This mode is used to initialize the module configuration, bit timing, and the CAN message filter. See msCAN12 Module Control Register (CMCR0) for a complete description of the SOFT_RESET mode.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller 18.8.4 Programmable Wake-Up Function The msCAN12 can be programmed to apply a low-pass filter function to the RxCAN input line while in SLEEP mode (see control bit WUPM in the module control register, msCAN12 Module Control Register (CMCR0)). This feature can be used to protect the msCAN12 from wake-up due to short glitches on the CAN bus lines. Such glitches can result from electromagnetic inference within noisy environments.
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Freescale Semiconductor, Inc. MSCAN Controller Clock System 18.10 Clock System Figure 18-7 shows the structure of the msCAN12 clock generation circuitry. With this flexible clocking scheme the msCAN12 is able to handle CAN bus rates ranging from 10 kbps up to 1 Mbps. CGM msCAN12 Freescale Semiconductor, Inc... SYSCLK CGMCANCLK CLKSRC EXTALi Prescaler (1...64) Time quanta clock CLKSRC Figure 18-7.
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Freescale Semiconductor, Inc. MSCAN Controller • Time segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. • Time segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Memory Map Figure 18-9. CAN Standard Compliant Bit Time Segment Settings Time Segment 1 TSEG1 Time Segment 2 TSEG2 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 2 3 4 5 6 7 8 1 2 3 4 5 6 7 Synchron. Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3 18.
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Freescale Semiconductor, Inc. MSCAN Controller 18.12 Programmer’s Model of Message Storage Freescale Semiconductor, Inc... The following section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Message Storage 18.12.1 Message Buffer Outline Figure 18-12 shows the common 13 byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 18-13. All bits of the 13 byte data structure are undefined out of reset. NOTE: The foreground receive buffer can be read anytime but can not be written.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Figure 18-13. Standard Identifier Mapping ADDR(1) REGISTER $01x0 IDR0 $01x1 IDR1 $01x2 IDR2 $01x3 IDR3 R/W R W R W R W R W BIT 7 6 5 4 3 2 1 BIT 0 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE(0) 1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively. 18.12.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Message Storage RTR — Remote transmission request This flag reflects the status of the Remote Transmission Request bit in the CAN frame. In case of a receive buffer it indicates the status of the received frame and allows to support the transmission of an answering frame in software. In case of a transmit buffer this flag defines the setting of the RTR bit to be sent. 0 = Data frame 1 = Remote frame 18.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller 18.12.4 Data Segment Registers (DSRn) The eight data segment registers contain the data to be transmitted or being received. The number of bytes to be transmitted or being received is determined by the data length code in the corresponding DLR. 18.12.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Control Registers 18.13 Programmer’s Model of Control Registers 18.13.1 Overview The programmer’s model has been laid out for maximum simplicity and efficiency. 18.13.
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Freescale Semiconductor, Inc. MSCAN Controller SLPRQ — SLEEP request This flag allows to request the msCAN12 to go into an internal powersaving mode (see msCAN12 SLEEP Mode). 0 = Wake-up – The msCAN12 will function normally. 1 = SLEEP request – The msCAN12 will go into SLEEP Mode when the CAN bus is idle, i.e. the module is not receiving a message and all transmit buffers are empty. SFTRES— SOFT_RESET Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Control Registers 18.13.3 msCAN12 Module Control Register (CMCR1) CMCR1 R $0101 W RESET Bit 7 0 6 0 5 0 4 0 3 0 0 0 0 0 0 2 1 Bit 0 LOOPB WUPM CLKSRC 0 0 0 LOOPB — Loop Back Self Test Mode Freescale Semiconductor, Inc... When this bit is set the msCAN12 performs an internal loop back which can be used for self test operation: the bit stream output of the transmitter is fed back to the receiver.
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Freescale Semiconductor, Inc. MSCAN Controller 18.13.4 msCAN12 Bus Timing Register 0 (CBTR0) CBTR0 R $0102 W RESET Bit 7 6 5 4 3 2 1 Bit 0 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 0 0 0 0 0 0 0 0 SJW1, SJW0 — Synchronization Jump Width Freescale Semiconductor, Inc... The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus (see Table 18-4).
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Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Control Registers 18.13.5 msCAN12 Bus Timing Register 1 (CBTR1) CBTR1 R $0103 W RESET Bit 7 6 5 4 3 2 1 Bit 0 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 0 0 0 0 0 0 0 0 SAMP — Sampling Freescale Semiconductor, Inc... This bit determines the number of samples of the serial bus to be taken per bit time.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown above). NOTE: The CBTR1 register can only be written if the SFTRES bit in CMCR0 is set. 18.13.6 msCAN12 Receiver Flag Register (CRFLG) All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position.
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Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Control Registers TWRNIF — Transmitter Warning Interrupt Flag This bit will be set when the msCAN12 goes into warning status due to the Transmit Error counter (TEC) exceeding 96 and neither one of the Error interrupt flags or the Bus-Off interrupt flag is set(1). If not masked, an Error interrupt is pending while this flag is set. 0 = No transmitter warning status has been reached. 1 = msCAN12 went into transmitter warning status.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller OVRIF — Overrun Interrupt Flag This bit will be set when a data overrun condition occurred. If not masked, an Error interrupt is pending while this flag is set. 0 = No data overrun has occurred. 1 = A data overrun has been detected. RXF — Receive Buffer Full The RXF flag is set by the msCAN12 when a new message is available in the foreground receive buffer.
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Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Control Registers RERRIE — Receiver Error Passive Interrupt Enable 0 = No interrupt will be generated from this event. 1 = A receiver error passive status event will result in an error interrupt. TERRIE — Transmitter Error Passive Interrupt Enable 0 = No interrupt will be generated from this event. 1 = A transmitter error passive status event will result in an error interrupt. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller 18.13.8 msCAN12 Transmitter Flag Register (CTFLG) The Abort Acknowledge flags are read only. The Transmitter Buffer Empty flags are read and clear only. A flag can be cleared by writing a1 to the corresponding bit position. Writing a zero has no effect on the flag setting. The Transmitter Buffer Empty flags each have an associated interrupt enable flag in the CTCR register. A hard or soft reset will reset the register.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Control Registers 0 = The associated message buffer is full (loaded with a message due for transmission). 1 = The associated message buffer is empty (not scheduled). NOTE: The CTFLG register is held in the reset state if the SFTRES bit in CMCR0 is set. 18.13.
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Freescale Semiconductor, Inc. MSCAN Controller 18.13.10 msCAN12 Identifier Acceptance Control Register (CIDAC) CIDAC R $0108 W RESET Bit 7 0 6 0 0 0 5 4 IDAM1 IDAM0 0 0 3 0 2 IDHIT2 1 IDHIT1 Bit 0 IDHIT0 0 0 0 0 IDAM1 – IDAM0 — Identifier Acceptance Mode Freescale Semiconductor, Inc... The CPU sets these flags to define the identifier acceptance filter organization (see Identifier Acceptance Filter). Table 18-7 summarizes the different settings.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Control Registers 18.13.11 msCAN12 Receive Error Counter (CRXERR) CRXERR R $010E W RESET Bit 7 RXERR7 6 RXERR6 5 RXERR5 4 RXERR4 3 RXERR3 2 RXERR2 1 RXERR1 Bit 0 RXERR0 0 0 0 0 0 0 0 0 This register reflects the status of the msCAN12 receive error counter. The register is read only. 18.13.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Figure 18-14. Identifier Acceptance Registers (1st bank) CIDAR0 $0110 CIDAR1 $0111 CIDAR2 $0112 CIDAR3 $0113 RESET R W R W R W R W Bit 7 6 5 4 3 2 1 Bit 0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 - - - - - - - - Figure 18-15.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller Programmer’s Model of Control Registers 18.13.14 msCAN12 Identifier Mask Registers (CIDMR0–7) The identifier mask register specifies which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. Figure 18-16.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. MSCAN Controller 18.13.15 msCAN12 Port CAN Control Register (PCTLCAN) PCTLCAN R $013D W RESET Bit 7 0 6 0 5 0 4 0 3 0 2 0 0 0 0 0 0 0 1 Bit 0 PUPCAN RDPCAN 0 0 The following bits control pins 7 through 2 of Port CAN when they are implemented externally. PUPCAN — Pull-Up Enable Port CAN 0 = Pull mode disabled for Port CAN. 1 = Pull mode enabled for Port CAN.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 19. Analog-to-Digital Converter 19.1 Contents 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 19.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 19.5 ATD Operational Modes . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Analog-to-Digital Converter Freescale Semiconductor, Inc... 19.2.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter Modes of Operation 19.3 Modes of Operation Freescale Semiconductor, Inc... Analog to digital conversions are performed in a variety of different programmable sequences referred to as conversion modes.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter • WAIT is executed (if the ASWAI bit is activated) • STOP is executed. The MCU can discover when result data is available in the result registers with an interrupt on sequence complete or by polling the conversion complete flags NOTE: • The SCF bit is set after the completion of each sequence. • The CCF bit associated with each result register is set when that register is loaded with result data.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter Functional Description 19.4.3 Sample and Hold Stage A Sample and Hold (S/H) stage accepts the analog signal from the input multiplexer and stores it as a capacitor charge on a storage node in the module. The sample process uses a three stage approach: 1. The input signal is sampled onto a sample capacitor (for 2 module clocks). 2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter programmable constant in order to generate the ATD module’s internal clock. One additional benefit of the prescaled clock feature is that it allows the user further control over the sample period (note that changing the module clock also affects conversion time). The prescaler is based on a 5 bit modulus counter and divides the PCLK by an integer value between 1 and 32.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Operation In Different MCU Modes can be performed. Note that powering up the module does not reset the module since the register file is not initialized. In power down mode, the control and result registers are still accessible. 19.5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter 19.6.2 WAIT Mode If the ASWAI control bit in ATDCTL2 is set, then the ATD responds to WAIT mode. If the ASWAI control bit is clear, then the ATD ignores the WAIT signal. The ATD response to the wait mode is to power down the module. In this mode, the MCU does not have access to the control, status or result registers. 19.6.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter General Purpose Digital Input Port Operation The ATD module reset function places the module back into an initialized state. If the module is performing a conversion sequence, both the current conversion and the sequence are terminated. The conversion complete flags are cleared and any pending interrupts are cancelled.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter 19.8 Application Considerations Note that the A/D converter’s accuracy is limited by the accuracy of the reference potentials. Noise on the reference potentials will result in noise on the digital output data stream: the reference potential lines do not reject reference noise. Freescale Semiconductor, Inc... The reference potential pins must have a low AC impedance path back to the source.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers 19.9.1 ATD Control Registers 0 &1 (ATDCTL0, ATDCTL1) ATD0CTL0/ATD1CTL0 — Reserved RESET: $0060/$01E0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Writes to this register will abort current conversion sequence. Read or write any time. ATD0CTL1/ATD1CTL1 — Reserved RESET: $0061/$01E1 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 WRITE: Write to this register has no meaning.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter This bit provides program on/off control over the ATD module allowing reduced MCU power consumption when the ATD is not being used. When reset to zero, the ADPU bit aborts any conversion sequence in progress. Because the analog electronics is turned off when powered down, the ATD requires a recovery time period when ADPU bit is enabled. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers exited, the ATD module powers up and continues operation. The module is not reset; the register file is not reinitialized; the conversion sequence is not restarted. When the module comes out of wait, it is recommended that a stabilization delay ( tSR) is allowed before new conversions are started. Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc. Analog-to-Digital Converter Freescale Semiconductor, Inc... Input Signal Vrl = 0 Volts Vrh = 5.12 Volts 5.120 Volts 5.100 5.080 8-Bit Codes 10-Bit Codes FF FF FE FFC0 FF00 FE00 2.580 2.560 2.540 81 80 7F 8100 8000 7F00 0.020 0.000 01 00 0100 0000 Table 19-2.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers ATD0CTL3/ATD1CTL3 — ATD Control Register 3 RESET: Bit 7 0 0 6 0 0 5 0 0 $0063/$01E3 4 0 0 3 S1C 0 2 FIFO 0 1 FRZ1 0 Bit 0 FRZ0 0 READ: any time WRITE: any time S1C — Conversion Sequence Length (Least Significant Bit) Freescale Semiconductor, Inc... This control bit works with control bit S8C in ATDCTL5 in determining how many conversion are performed per sequence. When the S1C bit is set, a sequence length of 1 is defined.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter Finally, which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode may or may not be useful in a particular application to track valid data. FRZ1, FRZ0 — Background Debug Freeze Enable Background debug freeze function allows the ATD module to pause when a breakpoint is encountered. Table 19-3 shows how FRZ1 and FRZ0 determine the ATD’s response to a breakpoint.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers RES10 — A/D Resolution Select 0 = 8-bit resolution selected 1 = 10-bit resolution selected This bit determines the resolution of the A/D converter: 8-bits or 10bits. The A/D converter has the accuracy of a 10-bit converter. However, if low resolution is adequate, the conversion can be speeded up by selecting 8-bit resolution. SMP[1:0] — Sample Time Select Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter Table 19-5. Clock Prescaler Values Prescale Value 00000 00001 00010 00011 00100 00101 00110 00111 01xxx 1xxxx Total Divisor Max PCLK(1) Min PCLK(2) ÷2 ÷4 ÷6 ÷8 ÷10 ÷12 ÷14 ÷16 4 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz Do Not Use 1. Maximum conversion frequency is 2 MHz.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers S8C S1C 0 0 1 0 1 X Number of Conversions per Sequence 4 1 8 Table 19-6. Conversion Sequence Length Coding Freescale Semiconductor, Inc... The result register assignments made to a conversion sequence follow a few simple rules. Normally, the first result is placed in the first register; the second result is placed in the second register, and so on.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter mode is required, the existing continuous sequence must be interrupted, the control registers modified, and a new conversion sequence initiated. MULT — Multi-Channel Sample Mode 0 = Sample only the specified channel 1 = Sample across many channels Freescale Semiconductor, Inc... When MULT is 0, the ATD sequence controller samples only from the specified analog input channel for an entire conversion sequence.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers Table 19-8 lists the special channels. The last column in the table denote the expected digital code that should be generated by the special conversion for 8-bit resolution. CC, CB, CA — Analog Input Channel Select Code Freescale Semiconductor, Inc... These bits select the analog input channel(s). Table 19-9 lists the coding used to select the various analog input channels.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter Table 19-10. Multichannel Mode Result Register Assignment (MULT=1) 4 channel conversion, External channels (S8C = 0, SC = 0) CC 0 0 0 0 CB 0 0 1 1 CA 0 1 0 1 ADR0 AN0 AN1 AN2 AN3 ADR1 AN1 AN2 AN3 AN4 ADR2 AN2 AN3 AN4 AN5 ADR3 AN3 AN4 AN5 AN6 1 0 0 AN4 AN5 AN6 AN7 1 0 1 AN5 AN6 AN7 AN0 1 1 0 AN6 AN7 AN0 AN1 1 1 1 AN7 AN0 AN1 AN2 1 0 0 VRH VRL MID 1 0 1 VRL MID 1 1 0 MID 1 1 1 S1C bit must be clear.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers Table 19-10.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter 19.9.5 ATDSTAT A/D Status Register The ATD Status registers contain the conversion complete flags and the conversion sequence counter. The status registers are read-only.
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Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers the result is available in result register ADR0; CCF1 is set when the second conversion in a sequence is complete and the result is available in ADR1, and so forth. Freescale Semiconductor, Inc... The conversion complete flags are cleared depending on the setting of the fast flag clear bit (AFFC in ATDCTL2).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter 19.9.6 ATDTEST Module Test Register (ATDTEST) The test registers implement various special (test) modes used to test the ATD module. The reset bit in ATDTEST1 is always read/write. The SAR (successive approximation register) can always be read but only written in special (test) mode. The functions implemented by the test registers are reserved for factory test.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter ATD Registers Resetting to idle mode defines the only exception of the reset control bit condition to the system reset condition. The reset control bit does not initialize the ADPU bit to its reset condition and therefore does not power down the module. This except allows the module to remain active for other test operations. 19.9.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Analog-to-Digital Converter 19.9.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 20. Development Support 20.1 Contents 20.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 20.3 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395 20.4 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .397 20.5 Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc. Development Support Table 20-1. IPIPE Decoding Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock(1) IPIPE[1:0] Mnemonic Meaning 0:0 — No Movement 0:1 LAT Latch Data From Bus 1:0 ALD Advance Queue and Load From Bus 1:1 ALL Advance Queue and Load From Latch Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Background Debug Mode 20.4 Background Debug Mode Background debug mode (BDM) is used for system development, incircuit testing, field testing, and programming. BDM is implemented in on-chip hardware and provides a full set of debug options. Because BDM control logic does not reside in the CPU, BDM hardware commands can be executed while the CPU is operating normally.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support In special single-chip mode, background operation is enabled and active immediately out of reset. This active case replaces the M68HC11 boot function, and allows programming a system with blank memory. While BDM is active, a set of BDM control registers are mapped to addresses $FF00 to $FF06. The BDM control logic uses these registers which can be read anytime by BDM logic, not user programs.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Background Debug Mode BKGD pin during host-to-target transmissions to speed up rising edges. Since the target does not drive the BKGD pin during this period, there is no need to treat the line as an open-drain signal during host-to-target transmissions.
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Freescale Semiconductor, Inc. Development Support Freescale Semiconductor, Inc... Figure 20-2 shows the host receiving a logic one from the target MC68HC912DT128A MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target B cycles).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Background Debug Mode Figure 20-3 shows the host receiving a logic zero from the target MC68HC912DT128A MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target MC68HC912DT128A finishes it.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Table 20-2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Background Debug Mode and executes them as they are received. The firmware commands are shown in Table 20-3. Table 20-3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support complete the requested write operation before a new serial command disturbs the BDM SHIFTER register. The external host should delay about 64 target BDMCLK cycles after a TRACE1 or GO command before starting any new serial command. This delay is needed because the BDM SHIFTER register is used as a temporary data holding register during the exit sequence to user code.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Background Debug Mode SHADOW word (location $0FC0); otherwise some regular EEPROM array locations will not be visible. At the next reset, the high byte of the SHADOW word is loaded into the EEMCR register. NOBDML bit in EEMCR will be cleared and BDM will not be operational. 4. Protect the SHADOW word by setting SHPROT bit in EEPROT register. 20.4.4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support is temporary storage for BDM commands.The CCRSAV register preserves the content of the CPU12 CCR while BDM is active. The only registers of interest to users are the STATUS register and the CCRSAV register.The other BDM registers are only used by the BDM firmware to execute commands.
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Freescale Semiconductor, Inc. Development Support Background Debug Mode BDMACT becomes set as active BDM mode is entered so that the BDM firmware ROM is enabled and put into the map. BDMACT is cleared by a carefully timed store instruction in the BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from the map. This bit has 4 clock cycles write delay. 0 = BDM is not active. BDM ROM and registers are not in map. 1 = BDM is active and waiting for serial commands.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support 1 = BDM system operates with ECLK. The WRITE_BD_BYTE@FF01 command that changes CLKSW including 150 cycles after the data portion of the command should be timed at the old speed. Beginning with the start of the next BDM command, the new clock can be used for timing BDM communications. If ECLK rate is slower than BDMCLK rate, CLKSW is ignored and BDM system is forced to operate with ECLK. 20.4.5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Background Debug Mode DATA — Data Flag - Shows that data accompanies the command.
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Freescale Semiconductor, Inc. Development Support R/W — Read/Write Flag 0 = Write 1 = Read Freescale Semiconductor, Inc... TTAGO — Trace, Tag, Go Field Table 20-5. TTAGO Decoding TTAGO Value Instruction 00 — 01 GO 10 TRACE1 11 TAGGO REGN — Register/Next Field Indicates which register is being affected by a command. In the case of a READ_NEXT or WRITE_NEXT command, index register X is preincriminated by 2 and the word pointed to by X is then read or written. Table 20-6.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Background Debug Mode 20.4.5.3 SHIFTER This 16-bit shift register contains data being received or transmitted via the serial interface. It is also used by the BDM firmware for temporary storage.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support 20.4.5.5 CCRSAV The CCRSAV register is used to save the CCR of the users program when entering BDM. It is also used for temporary storage in the BDM firmware. Read and write: all modes CCRSAV— BDM CCR Holding Register $FF06 BIT 7 CCR7 6 CCR6 5 CCR5 4 CCR4 3 CCR3 2 CCR2 1 CCR1 BIT 0 CCR0 X X X X X X X X RESET: NOTE 1 (1) 1. Initialized to equal the CPU12 CCR register by the firmware. 20.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Breakpoints 20.5.1 Breakpoint Modes Three modes of operation determine the type of breakpoint in effect. • Dual address-only breakpoints, each of which will cause a software interrupt (SWI) • Single full-feature breakpoint which will cause the part to enter background debug mode (BDM) • Dual address-only breakpoints, each of which will cause the part to enter BDM Breakpoints will not occur when BDM is active. 20.5.1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support • There is no hardware to enforce restriction of breakpoint operation if the BDM is not enabled. 20.5.1.3 BDM Dual Address Mode Dual address-only breakpoints, each of which cause the part to enter background debug mode. In the dual mode each address breakpoint is affected, consistent across modes, by the BKPM bit, the BKALE bit, and the BKxRW and BKxRWE bits.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Breakpoints To trace program flow, setting the BKPM bit causes address comparison of program data only. Control bits are also available that allow checking read/write matches. BRKCT0 — Breakpoint Control Register 0 RESET: $0020 Bit 7 6 5 4 3 2 1 Bit 0 BKEN1 BKEN0 BKPM 0 BK1ALE BK0ALE 0 0 0 0 0 0 0 0 0 0 Read and write anytime. This register is used to control the breakpoint logic.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support BK0ALE — Breakpoint 0 Range Control Valid in all modes. 0 = BRKAL will not be used to compare to the address bus. 1 = BRKAL will be used to compare to the address bus. Table 20-8.
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Freescale Semiconductor, Inc. Development Support Breakpoints BKMBL — Breakpoint Mask Low Disables the matching of the low byte of data when in full breakpoint mode. Used in conjunction with the BKDBE bit (which should be set) 0 = Low byte of data bus (bits 7:0) are compared to BRKDL 1 = Low byte is not used to in comparisons. BK1RWE — R/W Compare Enable Freescale Semiconductor, Inc... Enables the comparison of the R/W signal to further specify what causes a match.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support Table 20-9.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Development Support BRKDL — Breakpoint Data Register, Low Byte $0025 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 RESET: These bits are compared to the least significant byte of the data bus or the least significant byte of the address bus in dual address modes. BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be used in the breakpoint comparison. 20.
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Freescale Semiconductor, Inc. Development Support Table 20-10. Tag Pin Function TAGHI TAGLO Tag 1 1 no tag 1 0 low byte 0 1 high byte 0 0 both bytes Freescale Semiconductor, Inc... The tag follows program information as it advances through the queue. When a tagged instruction reaches the head of the queue, the CPU enters active background debugging mode rather than execute the instruction. Technical Data 420 MC68HC912DT128A — Rev 4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 21. Electrical Specifications 21.1 Contents 21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 21.3 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 21.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications 21.3 Tables of Data Table 21-1. Maximum Ratings(1) Rating Symbol Value Unit VDD, VDDA, VDDX −0.3 to +6.5 V Input voltage VIN −0.3 to +6.5 V Operating temperature range TA(2) TL to TH −40 to +85 −40 to +105 −40 to +125 °C Storage temperature range Tstg −55 to +150 °C IIN ±25 mA VDD−VDDX 6.5 V Supply voltage Current drain per pin(3) Excluding VDD and VSS VDD differential voltage 1.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Tables of Data Table 21-2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Table 21-3. DC Electrical Characteristics VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Characteristic Symbol Min Max Unit Input high voltage, all inputs VIH 0.7 × VDD VDD + 0.3 V Input low voltage, all inputs VIL VSS−0.3 0.2 × VDD V VOH VDD − 0.2 VDD − 0.8 — — V V VDD − 0.2 VDD − 0.8 — — V V — — VSS+0.2 VSS+0.4 V V — — VSS+0.2 VSS+0.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Tables of Data Table 21-4. Supply Current VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Frequency of Operation (E-clock) Characteristic Symbol Maximum total supply current RUN: Single-chip mode Expanded mode IDD WAIT: (All peripheral functions shut down) Single-chip mode Expanded mode WIDD Unit 2 MHz(1) 4 MHz(1) 8 MHz 20 30 30 50 55 90 mA mA 3 4 5 6.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Table 21-6. Analog Converter Characteristics (Operating) VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted Characteristic 8-bit resolution(1) Symbol Min Typical 1 count 8-bit absolute error,(2)2, 4, 8, and 16 ATD sample clocks 10-bit resolution(1) 20 −1 AE 5 AE –2.5 Unit mV +1 1 count 10-bit absolute error(2) 2, 4, 8, and 16 ATD sample clocks Max count mV 2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Tables of Data Table 21-8. ATD Maximum Ratings Characteristic Symbol Value Units ATD reference voltage VRH ≤ VDDA VRL ≥ VSSA VRH VRL −0.3 to +6.5 −0.3 to +6.5 V V VSS differential voltage |VSS−VSSA| 0.1 V VDD differential voltage VDD−VDDA VDDA−VDD 6.5 0.3 V V Reference to supply differential voltage VDDA−VRH VRH−VDDA VDDA−VRL VRL−VDDA 6.5 0.3 6.5 0.3 V VDDA−VINDC VINDC−VDDA 6.5 0.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Table 21-10. Flash EEPROM Characteristics VDD = 5.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Tables of Data Table 21-12. Control Timing Characteristic Symbol 8.0 MHz Unit Min Max fo 0.004 8.0 MHz E-clock period tcyc 0.125 250 µs External oscillator frequency feo 0.5 16.
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Freescale Semiconductor, Inc. NOTE: Reset timing is subject to change. INTERNAL ADDRESS MODA, MODB RESET ECLK EXTAL VDD 4098 tcyc FFFE FFFE FREE 1ST PIPE 2ND PIPE 3RD PIPE tPCSU 1ST EXEC FFFE PWRSTL tMPS FFFE FFFE Freescale Semiconductor, Inc... tMPH FREE 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Electrical Specifications Figure 21-2. POR and External Reset Timing Diagram Technical Data 430 MC68HC912DT128A — Rev 4.
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MOTOROLA MC68HC912DT128A — Rev 4.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com SP-6 SP-6 SP-8 SP-8 SP-9 SP-9 PWIRQ NOTES: 1. Edge Sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) 3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 tcyc if DLY = 0. 4. XIRQ with X bit in CCR = 1. 5. IRQ or (XIRQ with X bit in CCR = 0).
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Technical Data 432 SP – 2 NOTE: RESET also causes recovery from WAIT. R/W ADDRESS IRQ, XIRQ, OR INTERNAL INTERRUPTS ECLK SP – 6 . . . SP – 9 PC, IY, IX, B:A, , CCR STACK REGISTERS SP – 4 SP – 9 SP – 9 . . . SP – 9 SP – 9 tPCSU VECTOR ADDRESS tWRS FREE Freescale Semiconductor, Inc... 1ST PIPE 2ND PIPE 3RD PIPE 1ST EXEC Freescale Semiconductor, Inc. Electrical Specifications Figure 21-4. WAIT Recovery Timing Diagram MC68HC912DT128A — Rev 4.
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MOTOROLA VECT DATA MC68HC912DT128A — Rev 4.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com NOTES: 1. Edge sensitive IRQ pin (IRQE bit = 1) 2. Level sensitive IRQ pin (IRQE bit = 0) R/W VECTOR ADDR PWIRQ tPCSU ADDRESS OR INTERNAL INTERRUPT IRQ2, XIRQ, IRQ 1 ECLK PC SP – 2 PROG FETCH 1ST PIPE IY SP – 4 IX SP – 6 PROG FETCH 2ND PIPE B:A SP – 8 CCR SP – 9 PROG FETCH 3RD PIPE Freescale Semiconductor, Inc...
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Table 21-13. Peripheral Port Timing 8.0 MHz Characteristic Symbol Unit Min Max fo 0.004 8.0 MHz tcyc 0.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Tables of Data Table 21-14. Multiplexed Expansion Bus Timing VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted Characteristic(1), (2), (3), (4) Num Delay Symbol Frequency of operation (E-clock frequency) 8 MHz Unit Min Max fo 0.004 8.0 MHz 250 µs 1 Cycle timetcyc = 1/fo — tcyc 0.
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Freescale Semiconductor, Inc. Electrical Specifications 1 2 3 ECLK 16 17 18 19 20 21 Freescale Semiconductor, Inc... R/W LSTRB (W/O TAG ENABLED) 5 23 7 11 22 10 READ 12 ADDRESS ADDRESS/DATA MULTIPLEXED DATA 9 8 13 WRITE 15 ADDRESS 14 DATA 24 25 26 DBE NOTE: Measurement points shown are 20% and 70% of VDD Figure 21-8. Multiplexed Expansion Bus Timing Diagram Technical Data 436 MC68HC912DT128A — Rev 4.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Tables of Data Table 21-15. SPI Timing (VDD = 5.
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Freescale Semiconductor, Inc. Electrical Specifications SS1 (OUTPUT) 5 2 1 SCK (CPOL = 0) (OUTPUT) 4 13 SCK (CPOL = 1) (OUTPUT) 6 Freescale Semiconductor, Inc... 3 12 4 7 MISO (INPUT) MSB IN2 BIT 6 . 10 . . 1 LSB IN 10 MOSI (OUTPUT) MSB OUT2 11 BIT 6 . . . 1 LSB OUT 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Tables of Data SS (INPUT) 5 1 13 12 12 13 3 SCK (CPOL = 0) (INPUT) 4 2 4 SCK (CPOL = 1) (INPUT) 9 8 MISO (OUTPUT) 10 MSB OUT SLAVE 6 MOSI (INPUT) 11 11 BIT 6 . . . BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 7 MSB IN 1 LSB IN NOTE: Not defined but normally MSB of character just received.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Electrical Specifications Table 21-16. CGM Characteristics 5.0 Volts +/- 10% Characteristic Symbol Min. Max. Unit PLL reference frequency fREF 0.5 8 MHz Bus frequency fBUS 0.004 8 MHz VCO range fVCO 2.5 8 MHz fVCOMIN 0.5 2.5 MHz ∆trk 3% 4% — ∆Lock 0% 1.5% — Un-Lock Detection ∆unl 0.5% 2.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 22. Appendix: Changes from MC68HC912DG128 22.1 Contents 22.2 22.2.1 22.2.2 22.2.3 22.2.4 22.2.5 22.2.6 22.2.7 Significant changes from the MC68HC912DG128 (non-suffix device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: Changes from MC68HC912DG128 22.2.1.3 Flash Programming Procedure Programming of the flash is greatly simplified over previous HC12s. The read / verify / re-pulse programming algorithm is replaced by a much simpler method. 22.2.1.4 Flash Programming Time The most significant change resulting from the new flash technology is that the bulk erase and program times are now fixed.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: Changes from MC68HC912DG128 Significant changes from the MC68HC912DG128 (non-suffix device) to be set by programming an 10-bit time base pre-scalar into bits spread over two new registers, EEDIVH and EEDIVL. The EEDIVH and EEDIVL registers are volatile.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: Changes from MC68HC912DG128 22.2.4 WAIT mode This new version will correctly exit WAIT mode using short XIRQ or IRQ inputs. 22.2.5 KWU Filter The KWU filter will now ignore pulses shorter than 2 microseconds. 22.2.6 Port ADx Power must be applied to VDDA at all times even if the ADC is not being used. This is necessary for port AD0 and port AD1 to function correctly as digital inputs. 22.2.7 ATD 22.2.7.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: Changes from MC68HC912DG128 Significant changes from the MC68HC912DG128 (non-suffix device) 22.2.7.3 Additional Features ATD flexibility has been increased with additional signed result, data justification, single conversion selection and results location FIFO features. DJM & DSGN bits have been added to ATDxCTL2 register. Default values are compatible with MC68HC912DG128 functionality.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: Changes from MC68HC912DG128 22.2.7.6 SCF bit In SCAN mode (SCAN bit = 1 in ATDxCTL5) the Sequence Complete Flag (SCF bit in ATDSTATx) is set after completion of each conversion sequence. Previously it was only set at the end of the first conversion sequence. To ensure compatibility the application should not rely on this flag being set only once per SCAN mode. 22.2.7.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 23. Appendix: CGM Practical Aspects 23.1 Contents 23.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 23.3 Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . .447 23.4 Printed Circuit Board Guidelines. . . . . . . . . . . . . . . . . . . . . . .453 23.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: CGM Practical Aspects synchronizers would be jeopardized (e.g. the MCLK and XCLK clock generators). 23.3.2 Operation Under Adverse Environmental Conditions The normal operation for the PLL is the so-called ‘automatic bandwidth selection mode’ which is obtained by having the AUTO bit set in the PLLCR register.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: CGM Practical Aspects Practical Aspects For The PLL Usage acquisition (AUTO=0, ACQ=0 in the PLLCR register). In both equations, the power supply should be 5V. Start with the target loop bandwidth as a function of the other parameters, but obviously, nothing prevents the user from starting with the capacitor value for example. Also, remember that the smoothing capacitor is always assumed to be one tenth of the series capacitance value.
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Freescale Semiconductor, Inc. Appendix: CGM Practical Aspects Freescale Semiconductor, Inc... The filter components values are chosen from standard series (e.g. E12 for resistors). The operating voltage is assumed to be 5V (although there is only a minor difference between 3V and 5V operation). The smoothing capacitor Cp in parallel with R and C is set to be 1/10 of the value of C.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: CGM Practical Aspects Practical Aspects For The PLL Usage Table 23-1. Suggested 8MHz Synthesis PLL Filter Elements (Tracking Mode) Reference [MHz] SYNR Fbus [MHz] C [nF] R [kΩ] Loop Bandwidth [kHz] Bandwidth Limit [kHz] 0.614 $0C 7.98 100 4.3 1.1 157 0.614 $0C 7.98 4.7 20 5.3 157 0.614 $0C 7.98 1 43 11.5 157 0.614 $0C 7.98 0.33 75 20 157 0.8 $09 8.00 220 2.7 0.9 201 0.8 $09 8.00 10 12 4.
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Freescale Semiconductor, Inc. Appendix: CGM Practical Aspects Freescale Semiconductor, Inc... Table 23-2. Suggested 8MHz Synthesis PLL Filter Elements (Acquisition Mode) Reference [MHz] SYNR Fbus [MHz] C [nF] R [kΩ] Loop Bandwidth [kHz] Bandwidth Limit [kHz] 0.614 $0C 7.98 1000 0.43 1.2 157 0.614 $0C 7.98 47 2 5.5 157 0.614 $0C 7.98 10 4.3 12 157 0.614 $0C 7.98 3.3 7.5 21 157 0.8 $09 8.00 2200 0.27 0.9 201 0.8 $09 8.00 100 1.2 4.4 201 0.8 $09 8.00 22 2.
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Freescale Semiconductor, Inc. Appendix: CGM Practical Aspects Printed Circuit Board Guidelines 23.4 Printed Circuit Board Guidelines Freescale Semiconductor, Inc... Printed Circuit Boards (PCBs) are the board of choice for volume applications. If designed correctly, a very low noise system can be built on a PCB with consequently good EMI/EMC performances. If designed incorrectly, PCBs can be extremely noisy and sensitive modules, and the CGM could be disrupted.
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Freescale Semiconductor, Inc. Appendix: CGM Practical Aspects Freescale Semiconductor, Inc... spectrum. This is especially the case for the power supply pins close to the E port, when the E clock and/or the calibration clock are used. Technical Data 454 • On the general VDD power supply input, a ‘T’ low pass filter LCL can be used (e.g. 10µH-47µF-10µH). The ‘T’ is preferable to the ‘Π’ version as the exhibited impedance is more constant with respect to the VDD current.
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Freescale Semiconductor, Inc. Appendix: CGM Practical Aspects Printed Circuit Board Guidelines Freescale Semiconductor, Inc... In addition to the above general pieces of advice, the following guidelines should be followed for the CGM pins (but also more generally for any sensitive analog circuitry): • Parasitic capacitance on EXTAL is absolutely critical – probably the most critical layout consideration. The XTAL pin is not as sensitive.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Appendix: CGM Practical Aspects Technical Data 456 • Mount the PLL filter and oscillator components as close to the MCU as possible. • Do not allow the EXTAL and XTAL signals to interfere with the XFC node. Keep these tracks as short as possible. • Do not cross the CGM signals with any other signal on any level. • Remember that the reference voltage for the XFC filter is VDDPLL.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Section 24. Appendix: Information on MC68HC912DT128A Mask Set Changes 24.1 Contents 24.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 24.3 Oscillator – Major Changes . . . . . . . . . . . . . . . . . . . . . . . . . .457 24.4 Flash Protection Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 24.5 Clock Circuitry. . . . . . . . . . . . .
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: Information on MC68HC912DT128A 3. Change to the input ESD resistor from EXTAL to the gate of the oscillator amplifier to provide a parallel path, reducing parasitic phase shift in the oscillator. Additionally a new Pierce ("P") oscillator configurations has been added. See Section 13. Oscillator for full details. 24.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Appendix: Information on MC68HC912DT128A Mask Set Changes Oscillator – Minor Changes 24.7 Oscillator – Minor Changes The Automatic Level Control (ALC) capacitor reference was changed from VDD to VSS in the crystal oscillator circuit to improve noise immunity. Parasitic capacitance on internal signal lines has been decreased, thus decreasing sensitivity to external capacitance changes.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Appendix: Information on MC68HC912DT128A Technical Data 460 MC68HC912DT128A — Rev 4.0 Appendix: Information on MC68HC912DT128A Mask Set Changes For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Glossary A — See “accumulators (A and B or D).” accumulators (A and B or D) — Two 8-bit (A and B) or one 16-bit (D) general-purpose registers in the CPU. The CPU uses the accumulators to hold operands and results of arithmetic and logic operations. acquisition mode — A mode of PLL operation with large loop bandwidth. Also see ’tracking mode’.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary binary — Relating to the base 2 number system. binary number system — The base 2 number system, having two digits, 0 and 1. Binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary CGM — See “clock generator module (CGM).” clear — To change a bit from logic 1 to logic 0; the opposite of set. clock — A square wave signal used to synchronize events in a computer. clock generator module (CGM) — The CGM module generates a base clock signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit and/or phase-locked loop (PLL) circuit.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. The length of time required to execute an instruction is measured in CPU clock cycles. CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary fetch — To copy data from a memory location into the accumulator. firmware — Instructions and data programmed into nonvolatile memory. free-running counter — A device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission — Communication on a channel in which data can be sent and received simultaneously.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency — The time lag between instruction completion and data movement. least significant bit (LSB) — The rightmost digit of a binary number. logic 1 — A voltage level approximately equal to the input power voltage (VDD). logic 0 — A voltage level approximately equal to the ground voltage (VSS).
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary Motorola interconnect bus (MI-Bus) — The Motorola Interconnect Bus (MI Bus) is a serial communications protocol which supports distributed real-time control efficiently and with a high degree of noise immunity. Motorola scalable CAN (msCAN) — The Motorola scalable controller area network is a serial communications protocol that efficiently supports distributed real-time control with a very high level of data integrity.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted. In a system that uses odd parity, every byte is expected to have an odd number of logic 1s. In an even parity system, every byte should have an even number of logic 1s. In the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width — The amount of time a signal is on as opposed to being in its off state. pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a signal with a constant frequency. push — An instruction that copies the contents of the accumulator to the stack RAM.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary signed — A binary number notation that accommodates both positive and negative numbers. The most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the magnitude of the number. software — Instructions and data that control the operation of a microcontroller.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Glossary unbuffered — Utilizes only one register for data; new data overwrites current data. unimplemented memory location — A memory location that is not used. Writing to an unimplemented location has no effect. Reading an unimplemented location returns an unpredictable value. variable — A value that changes during the course of program execution. VCO — See "voltage-controlled oscillator.
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Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Glossary Technical Data 472 MC68HC912DT128A — Rev 4.0 Glossary For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Technical Data — MC68HC912DT128A Revision History This section lists the revision history of the document since the first release. Data for previous internal drafts is unavailable. 24.9 Changes in Rev. 4.0 Section Page (in Rev 3.0) Electrical Specifications 437 Description of change Clock (SCK) High or Low Time, Master, twsck changed from tcyc − 60 to tcyc − 30. 24.10 Changes from Rev 2.0 to Rev 3.0 Section Page (in Rev 3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Revision History Section Page (in Rev 3.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Revision History Changes from Rev 1.0 to Rev 2.0 24.11 Changes from Rev 1.0 to Rev 2.0 Section Page (in Rev 2.0) 30, 31 Description of change Figures 4 and 5, pin 97 changed to TEST and note added. 33 Note added about connection of power supplies. 35 Note about non-standard oscillator circuit expanded. 35 Additional paragraphs added covering DC bias. Registers 55 CD bit name corrected in ATD0CTL5.
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Freescale Semiconductor, Inc. Revision History Page (in Rev 1.0) MSI 236 Description of change Clarification of SP0DR register state on reset. Freescale Semiconductor, Inc... Section Technical Data 476 MC68HC912DT128A — Rev 4.0 Revision History For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.
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Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T.