Datasheet

Bus Control and Input/Output
Technical Data MC68HC912DT128A — Rev 4.0
110 Bus Control and Input/Output MOTOROLA
0 = PE4 is the external E-clock pin subject to the following
limitation: In single-chip modes, to get an E clock output signal,
it is necessary to have ESTR = 0 in addition to NECLK = 0. A
16-bit write to PEAR and MODE registers can configure all
three bits in one operation.
1 = PE4 is a general-purpose I/O pin.
LSTRE — Low Strobe (LSTRB
) Enable
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime. This bit has no effect in single-chip modes or normal
expanded narrow mode.
0 = PE3 is a general-purpose I/O pin.
1 = PE3 is configured as the LSTRB
bus-control output, provided
the MCU is not in single chip or normal expanded narrow
modes.
LSTRB
is used during external writes. After reset in normal expanded
mode, LSTRB
is disabled. If needed, it should be enabled before
external writes. External reads do not normally need LSTRB because
all 16 data bits can be driven even if the MCU only needs 8 bits of
data.
TAGLO
is a shared function of the PE3/LSTRB pin. In special
expanded modes with LSTRE set and the BDM tagging on, a zero at
the falling edge of E tags the instruction word low byte being read into
the instruction queue.
RDWE — Read/Write Enable
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime. This bit has no effect in single-chip modes.
0 = PE2 is a general-purpose I/O pin.
1 = PE2 is configured as the R/W
pin. In single chip modes, RDWE
has no effect and PE2 is a general-purpose I/O pin.
R/W is used for external writes. After reset in normal expanded mode,
it is disabled. If needed it should be enabled before any external
writes.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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