Datasheet

Resets and Interrupts
Interrupt Control and Priority Registers
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Resets and Interrupts 141
10.6 Interrupt Control and Priority Registers
IRQE — IRQ Select Edge Sensitive Only
0 = IRQ
configured for low-level recognition.
1 = IRQ
configured to respond only to falling edges (on pin
PE1/IRQ
).
IRQE can be read anytime and written once in normal modes. In
special modes, IRQE can be read anytime and written anytime,
except the first write is ignored.
IRQEN — External IRQ
Enable
The IRQ pin has an internal pull-up.
0 = External IRQ pin is disconnected from interrupt logic.
1 = External IRQ
pin is connected to interrupt logic.
$FFBC, $FFBD MSCAN 1 errors I bit
C1RIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
$BC
$FFBA, $FFBB MSCAN 1 receive I bit C1RIER (RXFIE) $BA
$FFB8, $FFB9 MSCAN 1 transmit I bit C1TCR (TXEIE[2:0]) $B8
$FFB6, $FFB7
(1)
MSCAN 2 wake-up I bit C2RIER (WUPIE) $B6
$FFB4, $FFB5
(1)
MSCAN 2 errors I bit
C2RIER (RWRNIE,
TWRNIE,
RERRIE, TERRIE,
BOFFIE, OVRIE)
$B4
$FFB2, $FFB3
(1)
MSCAN 2 receive I bit C2RIER (RXFIE) $B2
$FFB0, $FFB1
(1)
MSCAN 2 transmit I bit C2TCR (TXEIE[2:0]) $B0
$FF80–$FFAF Reserved I bit $80–$AE
1. MC68HC912DT128A only
INTCR — Interrupt Control Register $001E
Bit 7654321Bit 0
IRQEIRQENDLY00000
RESET: 01100000
Table 10-1. Interrupt Vector Map
Vector Address Interrupt Source
CCR
Mask
Local Enable
HPRIO Value to
Elevate
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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