Datasheet

Resets and Interrupts
Register Stacking
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Resets and Interrupts 147
10.9.7 Other Resources
The enhanced capture timer (ECT), pulse width modulation timer
(PWM), serial communications interfaces (SCI0 and SCI1), serial
peripheral interface (SPI), inter-IC bus (IIC), Motorola Scalable CANs
(MSCAN0 and MSCAN1) and analog-to-digital converters (ATD0 and
ATD1) are off after reset.
10.10 Register Stacking
Once enabled, an interrupt request can be recognized at any time after
the I bit in the CCR is cleared. When an interrupt service request is
recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles
required to complete the instruction. Some of the longer instructions can
be interrupted and will resume normally after servicing the interrupt.
When the CPU begins to service an interrupt, the instruction queue is
cleared, the return address is calculated, and then it and the contents of
the CPU registers are stacked as shown in Table 10-2.
After the CCR is stacked, the I bit (and the X bit, if an XIRQ
interrupt
service request is pending) is set to prevent other interrupts from
disrupting the interrupt service routine. The interrupt vector for the
highest priority source that was pending at the beginning of the interrupt
sequence is fetched, and execution continues at the referenced location.
At the end of the interrupt service routine, an RTI instruction restores the
content of all registers from information on the stack, and normal
program execution resumes.
Table 10-2. Stacking Order on Entry to Interrupts
Memory Location CPU Registers
SP – 2
RTN
H
: RTN
L
SP – 4
Y
H
: Y
L
SP – 6
X
H
: X
L
SP – 8 B : A
SP – 9 CCR
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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