Datasheet

Clock Functions
Technical Data MC68HC912DT128A — Rev 4.0
166 Clock Functions MOTOROLA
12.6.2 No Clock at Power-On Reset
The voltage level on VDDPLL determines how the MCU responds to an
external clock loss in this case.
With the VDDPLL supply voltage at VDD level, any reset sets the Clock
Monitor Enable bit (CME) and the PLLON bit and clears the NOLHM bit.
Therefore, if the MCU is powered up without an external clock, limp-
home mode is entered provided the MCU is in a normal mode of
operation.
Figure 12-4. No Clock at Power-On Reset
VDD
Power-On Detector
Clock Monitor Fail
EXTALi
13-stage counter
Internal reset
0 --> 4096
Limp-Home
(Clocked by XCLK)
BCSP
Reset: BCSP = 0
SYSCLK PLLCLK (L.H.) EXTALi
SYSCLK PLLCLK (Software check of Limp-Home Flag) EXTALi
(Slow EXTALi)
0 --> 4096
(Slow EXTALi)
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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