Datasheet

MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA List of Figures 17
Technical Data — MC68HC912DT128A
List of Figures
Figure Title Page
1-1 MC68HC912DT128A Block Diagram . . . . . . . . . . . . . . . . . . . .30
1-2 MC68HC912DG128A Block Diagram. . . . . . . . . . . . . . . . . . . .31
2-1 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3-1 Pin Assignments in 112-pin QFP for MC68HC912DT128A . . .42
3-2 Pin Assignments in 112-pin QFP for MC68HC912DG128A . . .43
3-3 112-pin QFP Mechanical Dimensions (case no. 987) . . . . . . .44
3-4 PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . .46
3-5 External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .48
6-1 MC68HC912DT128A Memory Map after reset. . . . . . . . . . . .100
6-2 MC68HC912DT128A Memory Paging . . . . . . . . . . . . . . . . . .101
11-1 STOP Key Wake-up Filter . . . . . . . . . . . . . . . . . . . . . . . . . . .155
12-1 Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .159
12-2 PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
12-3 Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . .164
12-4 No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . .166
12-5 STOP Exit and Fast STOP Recovery . . . . . . . . . . . . . . . . . . .168
12-6 Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182
12-7 Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . .183
12-8 Clock Chain for ECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
12-9 Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM . . . . . .185
13-1 MC68HC912DT128A Colpitts Oscillator Architecture. . . . . . .195
13-2 MC68HC912Dx128C Colpitts Oscillator Architecture. . . . . . .198
13-3 MC68HC912Dx128C Crystal with DC Blocking Capacitor . . .210
13-4 MC68HC912Dx128P Pierce Oscillator Architecture. . . . . . . .213
14-1 Block Diagram of PWM Left-Aligned Output Channel . . . . . .226
14-2 Block Diagram of PWM Center-Aligned Output Channel . . . .227
14-3 PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
15-1 Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .243
15-2 Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . .244
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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