Datasheet

List of Figures
Technical Data MC68HC912DT128A — Rev 4.0
18 List of Figures MOTOROLA
15-3 8-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . . .245
15-4 16-Bit Pulse Accumulators Block Diagram . . . . . . . . . . . . . . .246
15-5 Block Diagram for Port7 with Output compare / Pulse
Accumulator A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
15-6 C3F-C0F Interrupt Flag Setting . . . . . . . . . . . . . . . . . . . . . . .247
16-1 Multiple Serial Interface Block Diagram . . . . . . . . . . . . . . . . .278
16-2 Serial Communications Interface Block Diagram . . . . . . . . . .279
16-3 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . .291
16-4 SPI Clock Format 0 (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . .292
16-5 SPI Clock Format 1 (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . .293
16-6 Normal Mode and Bidirectional Mode. . . . . . . . . . . . . . . . . . .294
17-1 IIC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
17-2 IIC Transmission Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .304
17-3 IIC Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . .308
17-4 Flow-Chart of Typical IIC Interrupt Routine . . . . . . . . . . . . . .323
18-1 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
18-2 User Model for Message Buffer Organization. . . . . . . . . . . . .330
18-3 32-bit Maskable Identifier Acceptance Filters . . . . . . . . . . . . .333
18-4 16-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . .333
18-5 8-bit Maskable Acceptance Filters . . . . . . . . . . . . . . . . . . . . .334
18-6 SLEEP Request / Acknowledge Cycle . . . . . . . . . . . . . . . . . .340
18-7 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
18-8 Segments within the Bit Time . . . . . . . . . . . . . . . . . . . . . . . . .344
18-9 CAN Standard Compliant Bit Time Segment Settings . . . . . .345
18-10 msCAN12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
18-11 Message Buffer Organization . . . . . . . . . . . . . . . . . . . . . . . . .346
18-12 Receive/Transmit Message Buffer Extended Identifier. . . . . .347
18-13 Standard Identifier Mapping . . . . . . . . . . . . . . . . . . . . . . . . . .348
18-14 Identifier Acceptance Registers (1st bank) . . . . . . . . . . . . . . .364
18-15 Identifier Acceptance Registers (2nd bank) . . . . . . . . . . . . . .364
18-16 Identifier Mask Registers (1st bank) . . . . . . . . . . . . . . . . . . . .365
18-17 Identifier Mask Registers (2nd bank) . . . . . . . . . . . . . . . . . . .365
19-1 Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . .368
20-1 BDM Host to Target Serial Bit Timing. . . . . . . . . . . . . . . . . . .399
20-2 BDM Target to Host Serial Bit Timing (Logic 1) . . . . . . . . . . .399
20-3 BDM Target to Host Serial Bit Timing (Logic 0) . . . . . . . . . . .400
21-1 Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
21-2 POR and External Reset Timing Diagram . . . . . . . . . . . . . . .430
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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