Datasheet

Clock Functions
Technical Data MC68HC912DT128A — Rev 4.0
180 Clock Functions MOTOROLA
Read and write anytime.
A write to this register changes the SLWCLK frequency with minimum
delay (less than one SLWCLK cycle), thus allowing immediate tune-
up of the performance versus power consumption for the modules
using this clock. The frequency divide ratio is 2 times (SLOW), hence
the divide range is 2 to 126 (not on first pass products). When
SLOW = 0, the divider is bypassed. The generation of E, P and
M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus
to EXTALi Frequency is programmable to 2, 4, 8, 12, 16, 20, ..., 252,
by steps of 4. SLWCLK is a 50% duty cycle signal.
Bit 7654321Bit 0
0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDV0
RESET: 00000000
SLOW — Slow mode Divider Register $003E
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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