Datasheet

Clock Functions
Clock Divider Chains
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Clock Functions 183
Bus clock select bits BCSP and BCSS in the clock select register
(CLKSEL) determine which clock drives SYSCLK for the main system
including the CPU and buses. BCSS has no effect if BCSP is set. During
the transition, the clock select output will be held low and all CPU activity
will cease until the transition is complete.
The Module Clock Select bit MCS determines the clock used by the ECT
module and the baud rate generators of the SCIs. In limp-home mode,
the output of MCS is forced to 0, but the MCS bit reads the latched value.
It allows normal operation of the serial and timer subsystems at a fixed
reference frequency while allowing the CPU to operate at a higher,
variable frequency.
Figure 12-7. Clock Chain for SCI0, SCI1, RTI, COP
XCLK
SC0BD
MODULUS DIVIDER:
÷ 1, 2, 3, 4, 5, 6,...,8190, 8191
SCI0
RECEIVE
BAUD RATE (16x)
SCI0
TRANSMIT
BAUD RATE (1x)
BITS: RTR2, RTR1, RTR0
TO RTI
BITS: CR2, CR1, CR0
TO COP
÷ 16
SCI1
RECEIVE
BAUD RATE (16x)
SCI1
TRANSMIT
BAUD RATE (1x)
÷ 16
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
÷ 2
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
÷ 4
÷ 4
÷ 4
÷ 2
÷ 4
÷ 2
÷4
REGISTER: COPCTL
REGISTER: RTICTL
SC1BD
MODULUS DIVIDER:
÷ 1, 2, 3, 4, 5, 6,...,8190, 8191
REGISTER: RTICTL
BIT:RTBYP
÷ 2048
MCLK
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