Datasheet

Pulse Width Modulator
Technical Data MC68HC912DT128A — Rev 4.0
230 Pulse Width Modulator MOTOROLA
Read and write anytime.
PCLK3 — PWM Channel 3 Clock Select
0 = Clock B is the clock source for channel 3.
1 = Clock S1 is the clock source for channel 3.
PCLK2 — PWM Channel 2 Clock Select
0 = Clock B is the clock source for channel 2.
1 = Clock S1 is the clock source for channel 2.
PCLK1 — PWM Channel 1 Clock Select
0 = Clock A is the clock source for channel 1.
1 = Clock S0 is the clock source for channel 1.
PCLK0 — PWM Channel 0 Clock Select
0 = Clock A is the clock source for channel 0.
1 = Clock S0 is the clock source for channel 0.
If a clock select is changed while a PWM signal is being generated, a
truncated or stretched pulse may occur during the transition.
The following four bits apply in left-aligned mode only:
Table 14-1. Clock A and Clock B Prescaler
PCKA2
(PCKB2)
PCKA1
(PCKB1)
PCKA0
(PCKB0)
Value of
Clock A (B)
000 P
001 P ÷ 2
010 P ÷ 4
011 P ÷ 8
100 P ÷ 16
101 P ÷ 32
110 P ÷ 64
111P ÷ 128
PWPOL — PWM Clock Select and Polarity $0041
Bit 7 6 5 4 3 2 1 Bit 0
PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0
RESET: 0 0 0 0 0 0 0 0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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