Datasheet

Pulse Width Modulator
PWM Register Descriptions
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Pulse Width Modulator 239
PORTP can be read anytime.
PWM functions share port P pins 3 to 0 and take precedence over the
general-purpose port when enabled.
When configured as input, a read will return the pin level. For port bits 7
to 4 it will read zero because there are no available external pins.
When configured as output, a read will return the latched output data.
For port bits 7 to 4 it will read the last value written. A write will drive
associated pins only if configured for output and the corresponding PWM
channel is not enabled.
After reset, all pins are general-purpose, high-impedance inputs.
DDRP determines pin direction of port P when used for general-purpose
I/O.
DDRP[7:4] — This bits served as memory locations since there are no
corresponding port pins.
DDRP[3:0] — Data Direction Port P pin 0-3
0 = I/O pin configured as high impedance input
1 = I/O pin configured for output.
PORTP — Port P Data Register $0056
Bit 7 6 5 4 3 2 1 Bit 0
PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0
PWM – – – – PWM3 PWM2 PWM1 PWM0
RESET: – – – – – – – –
DDRP — Port P Data Direction Register $0057
Bit 7 6 5 4 3 2 1 Bit 0
DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0
RESET: 0 0 0 0 0 0 0 0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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