Datasheet

Enhanced Capture Timer
Timer Register Descriptions
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Enhanced Capture Timer 251
15.4 Timer Register Descriptions
Input/output pins default to general-purpose I/O lines until an internal
function which uses that pin is specifically enabled. The timer overrides
the state of the DDR to force the I/O state of each associated port line
when an output compare using a port line is enabled. In these cases the
data direction bits will have no affect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing
to this PORTT bit does not affect the pin but the data is stored in an
internal latch such that if the pin becomes available for general-purpose
output the driven level will be the last value written to the PORTT bit.
Read or write anytime.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
0 = The corresponding channel acts as an input capture
1 = The corresponding channel acts as an output compare.
Read anytime but will always return $00 (1 state is transient). Write
anytime.
TIOS — Timer Input Capture/Output Compare Select $0080
Bit 7 6 5 4 3 2 1 Bit 0
IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0
RESET: 0 0 0 0 0 0 0 0
CFORC — Timer Compare Force Register $0081
Bit 7 6 5 4 3 2 1 Bit 0
FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0
RESET: 0 0 0 0 0 0 0 0
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cale Semiconductor,
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