Datasheet

Enhanced Capture Timer
Technical Data MC68HC912DT128A — Rev 4.0
252 Enhanced Capture Timer MOTOROLA
FOC[7:0] — Force Output Compare Action for Channel 7-0
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare “n” to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set.
Read or write anytime.
The bits of OC7M correspond bit-for-bit with the bits of timer port
(PORTT). Setting the OC7Mn will set the corresponding port to be an
output port regardless of the state of the DDRTn bit when the
corresponding TIOSn bit is set to be an output compare. This does not
change the state of the DDRT bits. At successful OC7, for eachbit that is
set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
NOTE: OC7M has priority over output action on timer port enabled by OMn and
OLn bits in TCTL1 and TCTL2. If an OC7M bit is set, it prevents the
action of corresponding OM and OL bits on the selected timer port.
Read or write anytime.
The bits of OC7D correspond bit-for-bit with the bits of timer port
(PORTT). When a successful OC7 compare occurs, for each bit that is
set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
OC7M — Output Compare 7 Mask Register $0082
Bit 7 6 5 4 3 2 1 Bit 0
OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0
RESET: 0 0 0 0 0 0 0 0
OC7D — Output Compare 7 Data Register $0083
Bit 7 6 5 4 3 2 1 Bit 0
OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0
RESET: 0 0 0 0 0 0 0 0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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