Datasheet

Enhanced Capture Timer
Technical Data MC68HC912DT128A — Rev 4.0
256 Enhanced Capture Timer MOTOROLA
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge
detector circuits.
Read or write anytime.
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status
register. If cleared, the corresponding flag is disabled from causing a
hardware interrupt. If set, the corresponding flag is enabled to cause a
hardware interrupt.
Read or write anytime.
C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable.
TCTL3 — Timer Control Register 3 $008A
Bit 7 6 5 4 3 2 1 Bit 0
EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A
RESET: 0 0 0 0 0 0 0 0
TCTL4 — Timer Control Register 4 $008B
Bit 7 6 5 4 3 2 1 Bit 0
EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A
RESET: 0 0 0 0 0 0 0 0
Table 15-2. Edge Detector Circuit Configuration
EDGnB EDGnA Configuration
0 0 Capture disabled
0 1 Capture on rising edges only
1 0 Capture on falling edges only
1 1 Capture on any edge (rising or falling)
TMSK1 — Timer Interrupt Mask 1 $008C
Bit 7 6 5 4 3 2 1 Bit 0
C7I C6I C5I C4I C3I C2I C1I C0I
RESET: 0 0 0 0 0 0 0 0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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