Datasheet

Enhanced Capture Timer
Technical Data MC68HC912DT128A — Rev 4.0
258 Enhanced Capture Timer MOTOROLA
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
TFLG1 indicates when interrupt conditions have occurred. To clear a bit
in the flag register, write a one to the bit.
Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the
use of the ICOVW register ($AA) allows a timer interrupt to be generated
after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
Read anytime. Write used in the clearing mechanism (set bits cause
corresponding bits to be cleared). Writing a zero will not affect current
status of the bit.
When TFFCA bit in TSCR register is set, a read from an input capture or
a write into an output compare channel ($90–$9F) will cause the
corresponding channel flag CnF to be cleared.
C7F–C0F — Input Capture/Output Compare Channel “n” Flag.
Table 15-3. Prescaler Selection
PR2 PR1 PR0 Prescale Factor
000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128
TFLG1 — Main Timer Interrupt Flag 1 $008E
Bit 7 6 5 4 3 2 1 Bit 0
C7F C6F C5F C4F C3F C2F C1F C0F
RESET: 0 0 0 0 0 0 0 0
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cale Semiconductor,
I
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