Datasheet

Enhanced Capture Timer
Technical Data MC68HC912DT128A — Rev 4.0
260 Enhanced Capture Timer MOTOROLA
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when a
defined transition is sensed by the corresponding input capture edge
detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to
these registers have no meaning or effect during input capture. All timer
input capture/output compare registers are reset to $0000.
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit
pulse accumulators PAC3 and PAC2.
When PAEN is set, the PACA is enabled. The PACA shares the input pin
with IC7.
Read: any time
Write: any time
TC4 — Timer Input Capture/Output Compare Register 4 $0098–$0099
Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TC5 — Timer Input Capture/Output Compare Register 5 $009A–$009B
Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TC6 — Timer Input Capture/Output Compare Register 6 $009C–$009D
Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
TC7 — Timer Input Capture/Output Compare Register 7 $009E–$009F
Bit 7 6 5 4 3 2 1 Bit 0
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
PACTL — 16-Bit Pulse Accumulator A Control Register $00A0
BIT 7 6 5 4 3 2 1 BIT 0
0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI
RESET: 0 0 0 0 0 0 0 0
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cale Semiconductor,
I
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