Datasheet

Enhanced Capture Timer
Technical Data MC68HC912DT128A — Rev 4.0
262 Enhanced Capture Timer MOTOROLA
CLK1, CLK0 — Clock Select Bits
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock
from the timer is always used as an input clock to the timer counter.
The change from one selected clock to the other happens
immediately after these bits are written.
PAOVI — Pulse Accumulator A Overflow Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PAOVF is set
PAI — Pulse Accumulator Input Interrupt enable
0 = interrupt inhibited
1 = interrupt requested if PAIF is set
Read or write anytime. When the TFFCA bit in the TSCR register is set,
any access to the PACNT register will clear all the flags in the PAFLG
register.
PAOVF — Pulse Accumulator A Overflow Flag
Set when the 16-bit pulse accumulator A overflows from $FFFF to
$0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF
to $00.
This bit is cleared automatically by a write to the PAFLG register with
bit 1 set.
CLK1 CLK0 Clock Source
0 0 Use timer prescaler clock as timer counter clock
0 1 Use PACLK as input to timer counter clock
1 0 Use PACLK/256 as timer counter clock frequency
11
Use PACLK/65536 as timer counter clock
frequency
PAFLG — Pulse Accumulator A Flag Register $00A1
BIT 7 6 5 4 3 2 1 BIT 0
0 0 0 0 0 0 PAOVF PAIF
RESET: 0 0 0 0 0 0 0 0
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cale Semiconductor,
I
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