Datasheet

Enhanced Capture Timer
Timer Register Descriptions
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Enhanced Capture Timer 267
PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable
0 = 8-Bit Pulse Accumulator is disabled.
1 = 8-Bit Pulse Accumulator is enabled.
Read or write any time.
If enabled, after detection of a valid edge on input capture pin, the delay
counter counts the pre-selected number of M clock (module clock)
cycles, then it will generate a pulse on its output. The pulse is generated
only if the level of input signal, after the preset delay, is the opposite of
the level before the transition.This will avoid reaction to narrow input
pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be
longer than the selected counter delay.
DLYx — Delay Counter Select
Read or write any time.
DLYCT — Delay Counter Control Register $00A9
BIT 7 6 5 4 3 2 1 BIT 0
0 0 0 0 0 0 DLY1 DLY0
RESET: 0 0 0 0 0 0 0 0
DLY1 DLY0 Delay
0 0 Disabled (bypassed)
0 1 256M clock cycles
1 0 512M clock cycles
1 1 1024 M clock cycles
ICOVW — Input Control Overwrite Register $00AA
BIT 7 6 5 4 3 2 1 BIT 0
NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0
RESET: 0 0 0 0 0 0 0 0
Frees
cale Semiconductor,
I
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