Datasheet

Enhanced Capture Timer
Technical Data MC68HC912DT128A — Rev 4.0
270 Enhanced Capture Timer MOTOROLA
0 = Queue Mode of Input Capture is enabled.
The main timer value is memorized in the IC register by a valid
input pin transition.
With a new occurrence of a capture, the value of the IC register
will be transferred to its holding register and the IC register
memorizes the new timer value.
1 = Latch Mode is enabled. Latching function occurs when
modulus down-counter reaches zero or a zero is written into
the count register MCCNT (see Buffered IC Channels).
With a latching event the contents of IC registers and 8-bit
pulse accumulators are transferred to their holding registers.
8-bit pulse accumulators are cleared.
Read: any time
Write: only in special mode (SMOD = 1).
TCBYP — Main Timer Divider Chain Bypass
0 = Normal operation
1 = For testing only. The 16-bit free-running timer counter is divided
into two 8-bit halves and the prescaler is bypassed. The clock
drives both halves directly.
When the high byte of timer counter TCNT ($84) overflows
from $FF to $00, the TOF flag in TFLG2 ($8F) will be set.
Read: any time (inputs return pin level; outputs return data register
contents)
TIMTST — Timer Test Register $00AD
BIT 7 6 5 4 3 2 1 BIT 0
0 0 0 0 0 0 TCBYP 0
RESET: 0 0 0 0 0 0 0 0
PORTT — Timer Port Data Register $00AE
BIT 7 6 5 4 3 2 1 BIT 0
PORT PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0
TIMER I/OC7 I/OC6 I/OC5 I/OC4 I/OC3 I/OC2 I/OC1 I/OC0
RESET: - - - - - - - -
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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