Datasheet

Multiple Serial Interface
Technical Data MC68HC912DT128A — Rev 4.0
278 Multiple Serial Interface MOTOROLA
16.3 Block diagram
Figure 16-1. Multiple Serial Interface Block Diagram
16.4 Serial Communication Interface (SCI)
Two serial communication interfaces are available on the
MC68HC912DT128A. These are NRZ format (one start, eight or nine
data, and one stop bit) asynchronous communication systems with
independent internal baud rate generation circuitry and SCI transmitters
and receivers. They can be configured for eight or nine data bits (one of
which may be designated as a parity bit, odd or even). If enabled, parity
is generated in hardware for transmitted and received data. Receiver
parity errors are flagged in hardware. The baud rate generator is based
on a modulus counter, allowing flexibility in choosing baud rates. There
is a receiver wake-up feature, an idle line detect feature, a loop-back
mode, and various error detection features. Two port pins for each SCI
provide the external interface for the transmitted data (TXD) and the
received data (RXD).
For a faster wake-up out of WAIT mode by a received SCI message,
both SCI have the capability of sending a receiver interrupt, if enabled,
when RAF (receiver active flag) is set. For compatibility with other
M68HC12 products, this feature is active only in WAIT mode and is
disabled when VDDPLL supply is at V
SS
level.
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
SCI0
SCI1
SPI
DDRS/IOCTLR
PORT S I/O DRIVERS
MSI
RxD0
TxD0
RxD1
TxD1
MISO/SISO
MOSI/MOMI
SCK
CS
/SS
HC12A4 MSI BLOCK
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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