Datasheet

Multiple Serial Interface

Technical Data MC68HC912DT128A — Rev 4.0

286 Multiple Serial Interface MOTOROLA

The bits in these registers are set by various conditions in the SCI

hardware and are automatically cleared by special acknowledge

sequences. The receive related flag bits in SCxSR1 (RDRF, IDLE,

OR, NF, FE, and PF) are all cleared by a read of the SCxSR1 register

followed by a read of the transmit/receive data register low byte.

However, only those bits which were set when SCxSR1 was read will

be cleared by the subsequent read of the transmit/receive data

are cleared by a read of the SCxSR1 register followed by a write to

the transmit/receive data register low byte.

Read anytime (used in auto clearing mechanism). Write has no

meaning or effect.

TDRE — Transmit Data Register Empty Flag

New data will not be transmitted unless SCxSR1 is read before writing

to the transmit data register. Reset sets this bit.

0 = SCxDR busy

1 = Any byte in the transmit data register is transferred to the serial

shift register so new data may now be written to the transmit

data register.

TC — Transmit Complete Flag

Flag is set when the transmitter is idle (no data, preamble, or break

transmission in progress). Clear by reading SCxSR1 with TC set and

then writing to SCxDR.

0 = Transmitter busy

1 = Transmitter is idle

SC0SR1/SC1SR1 — SCI Status Register 1 $00C4/$00CC

Bit 7654321Bit 0

TDRE TC RDRF IDLE OR NF FE PF

RESET:11000000

Frees

cale Semiconductor,

Freescale Semiconductor, Inc.

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