Datasheet

Multiple Serial Interface
Serial Peripheral Interface (SPI)
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Multiple Serial Interface 293
Figure 16-5. SPI Clock Format 1 (CPHA = 1)
16.5.3 SS Output
Available in master mode only, SS output is enabled with the SSOE bit
in the SP0CR1 register if the corresponding DDRS is set. The SS output
pin will be connected to the SS
input pin of the external slave device. The
SS
output automatically goes low for each transmission to select the
external device and it goes high during each idling state to deselect
external devices.
t
L
t
T
for t
T
, t
l
, t
L
Minimum 1/2 SCK
t
I
t
L
If next transfer begins here
Begin End
SCK (CPOL=0)
SAMPLE I
CHANGE O
SEL SS
(O)
Transfer
SCK (CPOL=1)
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
LSB
MSB
Bit 5
Bit 2
Bit 6
Bit 1
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
CHANGE O
SEL SS
(I)
(MOSI pin)
(MISO pin)
(Master only)
(MOSI/MISO)
HC12 SPI CLOCK FORM 1
Table 16-3. SS Output Selection
DDRS7 SSOE Master Mode Slave Mode
00SS
Input with MODF Feature SS Input
01 Reserved SS
Input
1 0 General-Purpose Output SS
Input
11 SS
Output SS Input
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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