Datasheet

Multiple Serial Interface
Technical Data MC68HC912DT128A — Rev 4.0
294 Multiple Serial Interface MOTOROLA
16.5.4 Bidirectional Mode (MOMI or SISO)
In bidirectional mode, the SPI uses only one serial data pin for external
device interface. The MSTR bit decides which pin to be used. The MOSI
pin becomes serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
direction of each serial I/O pin depends on the corresponding DDRS bit.
16.5.5 Register Descriptions
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to Operating Modes.
Read or write anytime.
SPIE — SPI Interrupt Enable
0 = SPI interrupts are inhibited
Figure 16-6. Normal Mode and Bidirectional Mode
When SPE=1 Master Mode
MSTR=1
Slave Mode
MSTR=0
Normal
Mode
SPC0=0
SWOM enables open drain output. SWOM enables open drain output.
Bidirectional
Mode
SPC0=1
SWOM enables open drain output. PS4 becomes GPIO. SWOM enables open drain output. PS5 becomes GPIO.
SPI
MO
MI
DDRS5
Serial Out
Serial In
SPI
SI
SO
Serial In
Serial Out
DDRS4
SPI
MOMI
PS4
DDRS5
Serial Out
Serial In
SPI
PS5
SISO
DDRS4
Serial In
Serial Out
SP0CR1 — SPI Control Register 1 $00D0
Bit 7654321Bit 0
SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF
RESET: 0 0 0 0 0 1 0 0
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cale Semiconductor,
I
Freescale Semiconductor, Inc.
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