Datasheet

Multiple Serial Interface
Serial Peripheral Interface (SPI)
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Multiple Serial Interface 297
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
These bits are used to specify the SPI clock rate.
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
SPIF is set after the eighth SCK cycle in a data transfer and it is
cleared by reading the SP0SR register (with SPIF set) followed by an
access (read or write) to the SPI data register.
SP0BR — SPI Baud Rate Register $00D2
Bit 7654321Bit 0
0 0 0 0 0 SPR2 SPR1 SPR0
RESET: 0 0 0 0 0 0 0 0
Table 16-4. SPI Clock Rate Selection
SPR2 SPR1 SPR0
E Clock
Divisor
Frequency at
E Clock = 4 MHz
Frequency at
E Clock = 8 MHz
0 0 0 2 2.0 MHz 4.0 MHz
0 0 1 4 1.0 MHz 2.0 MHz
0 1 0 8 500 kHz 1.0 MHz
0 1 1 16 250 kHz 500 KHz
1 0 0 32 125 kHz 250 KHz
1 0 1 64 62.5 kHz 125 KHz
1 1 0 128 31.3 kHz 62.5 KHz
1 1 1 256 15.6 kHz 31.3 KHz
SP0SR — SPI Status Register $00D3
Bit 7654321Bit 0
SPIFWCOL0MODF0000
RESET: 00000000
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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