Datasheet
General Description
Technical Data MC68HC912DT128A — Rev 4.0
30 General Description MOTOROLA
1.5 MC68HC912DT128A Block Diagram
Figure 1-1. MC68HC912DT128A Block Diagram
TxCAN0
DDRH
PORTH
KWH4
KWH3
KWH2
KWH1
KWH0
KWH7
KWH6
KWH5
PH4
PH3
PH2
PH1
PH0
PH7
PH6
PH5
DDRJ
PORTJ
PJ4
PJ3
PJ2
PJ1
PJ0
PJ7
PJ6
PJ5
KWJ4
KWJ3
KWJ2
KWJ1
KWJ0
KWJ7
KWJ6
KWJ5
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
DDRT
PORT T
128K byte flash EEPROM
8K byte RAM
PORT E
Enhanced
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
SPI
DDRS
PORT S
PORT AD1
PE1
PE2
PE4
PE5
PE6
PE3
PAD13
PAD14
PAD15
PAD16
PAD17
VDDA
VSSA
VRH1
VRL1
PAD10
PAD11
PAD12
RESET
EXTAL
XTAL
PW0
PW1
PW2
PW3
PWM
DDRP
PORT P
PP0
PP1
PP2
PP3
VDD ×2
VSS ×2
SCI0
RxD0
TxD0
RxD1
TxD1
SDI/MISO
SDO/MOSI
SCK
SS
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
2K byte EEPROM
PE0
PE7
AN13
AN14
AN15
AN16
AN17
VDDA
VSSA
VRH1
VRL1
AN10
AN11
AN12
BKGD
ECLK
R/W
LSTRB
MODA
MODB
XIRQ
DBE/CAL
capture
timer
Lite
IRQ
SCI1
integration
module
(LIM)
CPU12
Periodic interrupt
COP watchdog
Clock monitor
Single-wire
background
debug module
Breakpoints
PLL
VSSPLL
XFC
VDDPLL
CAN0
RxCAN0
DDRA
PORT A
DDRB
PORT B
PA 4
PA 3
PA 2
PA 1
PA 0
PA 7
PA 6
PA 5
PB4
PB3
PB2
PB1
PB0
PB7
PB6
PB5
DATA15
Multiplexed Address/Data Bus
A
D
D
R
1
5
A
D
D
R
1
4
A
D
D
R
1
3
A
D
D
R
1
2
A
D
D
R
1
1
A
D
D
R
1
0
A
D
D
R
9
A
D
D
R
8
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
A
D
D
R
7
A
D
D
R
6
A
D
D
R
5
A
D
D
R
4
A
D
D
R
3
A
D
D
R
2
A
D
D
R
1
A
D
D
R
0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ATD1
PORT AD0
PAD03
PAD04
PAD05
PAD06
PAD07
VRH0
VRL0
PAD00
PAD01
PAD02
AN03
AN04
AN05
AN06
AN07
VDDA
VSSA
VRH0
VRL0
AN00
AN01
AN02
ATD0
PPAGE
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Wide
bus
Narrow bus
VDDX ×2
VSSX ×2
Power for internal circuitry
Power for I/O drivers
PK0
PK1
PK2
PK3
VSTBY
IIC
SCL
SDA
PIB7
PIB6
DDRK
PORT K
PIX0
PIX1
PIX2
ECS
KWU
Clock
Generation
module
PK7
I/O
TxCAN1
CAN1
RxCAN1
TxCAN2
CAN2
RxCAN2
DDRIB
PORT IB
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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