Datasheet

Inter IC Bus
Technical Data MC68HC912DT128A — Rev 4.0
308 Inter IC Bus MOTOROLA
Figure 17-3. IIC Clock Synchronization
17.5.8 Handshaking
The clock synchronization mechanism can be used as a handshake in
data transfer. Slave devices may hold the SCL low after completion of
one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
17.5.9 Clock Stretching
The clock synchronization mechanism can be used by slaves to slow
down the bit rate of a transfer. After the master has driven SCL low the
slave can drive SCL low for the required period and then release it. If the
slave SCL low period is greater than the master SCL low period then the
resulting SCL bus signal low period is stretched.
SCL1
SCL2
SCL
Internal Counter Reset
WAIT
Start Counting High Period
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cale Semiconductor,
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