Datasheet

Inter IC Bus
IIC Register Descriptions
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Inter IC Bus 309
17.6 IIC Register Descriptions
.
Read and write anytime
This register contains the address the IIC will respond to when
addressed as a slave; note that it is not the address sent on the bus
during the address transfer
ADR7–ADR1 — Slave Address
Bit 1 to bit 7 contain the specific slave address to be used by the IIC
module.
The default mode of IIC is slave mode for an address match on the
bus.
Read and write anytime
IBC5–IBC0 — IIC Bus Clock Rate 5–0
This field is used to prescale the clock for bit rate selection. The bit
clock generator is implemented as a prescaled shift register - IBC5-3
select the prescaler divider and IBC2-0 select the shift register tap
point. The IBC bits are decoded to give the Tap and Prescale values
as shown in Table 17-1.
NOTE: At 8 MHz system bus frequency, the IIC bus frequency will slow down by
as much as 5%. However, the communications rate of the IIC system will
be automatically adjusted to a slower rate.
IBAD — IIC Bus Address Register $00E0
Bit 7654321Bit 0
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0
RESET: 00000000
IBFD — IIC Bus Frequency Divider Register $00E1
Bit 7654321Bit 0
00IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
RESET: 0 0 0 0 0 0 0 0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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