Datasheet

Inter IC Bus
Technical Data MC68HC912DT128A — Rev 4.0
318 Inter IC Bus MOTOROLA
Read and write anytime
DDRIB[7:2]— Port IB [7:2] Data direction
Each bit determines the primary direction for each pin configured as
general-purpose I/O.
0 = Associated pin is a high-impedance input.
1 = Associated pin is an output.
DDRIB[5:0] — These bits served as memory locations since there are
no corresponding external port pins for MC68HC912DT128A.
17.7 IIC Programming Examples
17.7.1 Initialization Sequence
Reset will put the IIC Bus Control Register to its default status. Before
the interface can be used to transfer serial data, an initialization
procedure must be carried out, as follows:
1. Update the Frequency Divider Register (IBFD) and select the
required division ratio to obtain SCL frequency from system clock.
2. Update the IIC Bus Address Register (IBAD) to define its slave
address.
3. Set the IBEN bit of the IIC Bus Control Register (IBCR) to enable
the IIC interface system.
4. Modify the bits of the IIC Bus Control Register (IBCR) to select
Master/Slave mode, Transmit/Receive mode and interrupt enable
or not.
DDRIB — Data Direction for Port IB Register $00E7
Bit 76 5 4 3 2 1Bit 0
DDRIB7 DDRIB6 DDRIB5 DDRIB4 DDRIB3 DDRIB2 DDRIB1 DDRIB0
RESET: 0 0 0 0 0 0 0 0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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