Datasheet

Inter IC Bus
Technical Data MC68HC912DT128A — Rev 4.0
320 Inter IC Bus MOTOROLA
monitor the IBIF bit rather than the TCF bit since their operation is
different when arbitration is lost.
Note that when an interrupt occurs at the end of the address cycle the
master will always be in transmit mode, i.e. the address is transmitted. If
master receive mode is required, indicated by R/W
bit in IBDR, then the
Tx/Rx
bit should be toggled at this stage.
During slave mode address cycles (IAAS=1) the SRW bit in the status
register is read to determine the direction of the subsequent transfer and
the Tx/Rx
bit is programmed accordingly. For slave mode data cycles
(IAAS=0) the SRW bit is not valid, the Tx/Rx
bit in the control register
should be read to determine the direction of the current transfer.
The following is an example of a software response by a 'master
transmitter' in the interrupt routine (see Figure 17-4).
17.7.4 Generation of STOP
A data transfer ends with a STOP signal generated by the 'master'
device. A master transmitter can simply generate a STOP signal after all
the data has been transmitted. The following is an example showing how
a stop condition is generated by a master transmitter.
If a master receiver wants to terminate a data transfer, it must inform the
slave transmitter by not acknowledging the last byte of data which can
ISR BCLR IBSR,#$02 ;CLEAR THE IBIF FLAG
BRCLR IBCR,#$20,SLAVE ;BRANCH IF IN SLAVE MODE
BRCLR IBCR,#$10,RECEIVE ;BRANCH IF IN RECEIVE MODE
BRSET IBSR,#$01,END ;IF NO ACK, END OF TRANSMISSION
TRANSMIT MOVB DATABUF,IBDR ;TRANSMIT NEXT BYTE OF DATA
MASTX TST TXCNT ;GET VALUE FROM THE
;TRANSMITING COUNTER
BEQ END ;END IF NO MORE DATA
BRSET IBSR,#$01,END ;END IF NO ACK
MOVB DATABUF,IBDR ;TRANSMIT NEXT BYTE OF DATA
DEC TXCNT ;DECREASE THE TXCNT
BRA EMASTX ;EXIT
END BCLR IBCR,#$20 ;GENERATE A STOP CONDITION
EMASTX RTI ;RETURN FROM INTERRUPT
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...