Datasheet

Development Support
Technical Data MC68HC912DT128A — Rev 4.0
400 Development Support MOTOROLA
Figure 20-2 shows the host receiving a logic one from the target
MC68HC912DT128A MCU. Since the host is asynchronous to the target
MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The
host holds the BKGD pin low long enough for the target to recognize it
(at least two target B cycles). The host must release the low drive before
the target MCU drives a brief active-high speed-up pulse seven cycles
after the perceived start of the bit time. The host should sample the bit
level about ten cycles after it started the bit time.
Figure 20-3. BDM Target to Host Serial Bit Timing (Logic 0)
10 CYCLES
BDMCLK
(TARGET
MCU)
EARLIEST
START OF
NEXT BIT
BKGD PIN
PERCEIVED
START OF BIT TIME
10 CYCLES
HOST SAMPLES
BKGD PIN
HOST
DRIVE TO
BKGD PIN
TARGET MCU
DRIVE AND
SPEEDUP PULSE
HIGH-IMPEDANCE
SPEEDUP PULSE
HC12A4 BDM TARGET TO HOST TIM 0
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...