Datasheet

Electrical Specifications
Tables of Data
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Electrical Specifications 429
NOTE: RESET is recognized during the first clock cycle it is held low. Internal
circuitry then drives the pin low for 16 clock cycles, releases the pin, and
samples the pin level 9 cycles later to determine the source of the
interrupt.
Figure 21-1. Timer Inputs
Table 21-12. Control Timing
Characteristic Symbol
8.0 MHz
Unit
Min Max
Frequency of operation
f
o
0.004 8.0 MHz
E-clock period
t
cyc
0.125 250 µs
External oscillator frequency
f
eo
0.5
16.0
(1)
MHz
Processor control setup time
t
PCSU
= t
cyc
/2+ 30
t
PCSU
92 —
ns
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be preempted by internal reset)
PW
RSTL
32
2
—
—
t
cyc
t
cyc
Mode programming setup time
t
MPS
4—
t
cyc
Mode programming hold time
t
MPH
20 — ns
Interrupt pulse width, IRQ
edge-sensitive mode
PW
IRQ
= 2t
cyc
+ 20
PW
IRQ
270 — ns
Wait recovery startup time
t
WRS
— 4 cycles
Timer input capture pulse width
PW
TIM
270 — ns
1. When using a resonator (quartz or ceramic), see Table 21-17 for allowable values.
PT7
2
PT7
1
PT[7:0]
2
PT[7:0]
1
NOTES:
1. Rising edge sensitive input
2. Falling edge sensitive input
PW
TIM
PW
PA
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
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