Datasheet

Electrical Specifications
Tables of Data
MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Electrical Specifications 437
Table 21-15. SPI Timing
(V
DD
= 5.0 Vdc ±10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
, 200 pF load on all SPI pins)
(1)
Num
Function Symbol Min Max Unit
Operating Frequency
Master
Slave
f
op
1/256
1/256
1/2
1/2
f
eclk
SCK Period
Master
Slave
t
sck
2
2
256
—
t
cyc
t
cyc
Enable Lead Time
Master
Slave
t
lead
1/2
1
—
—
t
sck
t
cyc
Enable Lag Time
Master
Slave
t
lag
1/2
1
—
—
t
sck
t
cyc
Clock (SCK) High or Low Time
Master
Slave
t
wsck
t
cyc
− 30
t
cyc
− 30
128 t
cyc
—
ns
ns
Sequential Transfer Delay
Master
Slave
t
td
1/2
1
—
—
t
sck
t
cyc
Data Setup Time (Inputs)
Master
Slave
t
su
30
30
—
—
ns
ns
Data Hold Time (Inputs)
Master
Slave
t
hi
0
30
—
—
ns
ns
Slave Access Time
t
a
—1
t
cyc
Slave MISO Disable Time
t
dis
—1
t
cyc
Data Valid (after SCK Edge)
Master
Slave
t
v
—
—
50
50
ns
ns
Data Hold Time (Outputs)
Master
Slave
t
ho
0
0
—
—
ns
ns
Rise Time
Input
Output
t
ri
t
ro
—
—
t
cyc
− 30
30
ns
ns
Fall Time
Input
Output
t
fi
t
fo
—
—
t
cyc
− 30
30
ns
ns
1. All AC timing is shown with respect to 20% V
DD
and 70% V
DD
levels unless otherwise noted.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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