Datasheet

MC68HC912DT128A — Rev 4.0 Technical Data
MOTOROLA Revision History 473
Technical Data — MC68HC912DT128A
Revision History
This section lists the revision history of the document since the first
release. Data for previous internal drafts is unavailable.
24.9 Changes in Rev. 4.0
24.10 Changes from Rev 2.0 to Rev 3.0
Section Page (in Rev 3.0) Description of change
Electrical
Specifications
437
Clock (SCK) High or Low Time, Master, t
wsck
changed from
t
cyc
− 60 to t
cyc
− 30.
Section Page (in Rev 3.0) Description of change
Pinout and Signal
Descriptions
42, 43 Note about TEST pin updated
46 PLL loop filter connections diagram (Figure 3-4) updated
48
Note added about consideration of crystal selection due to EMC
emissions
54 Description of TEST pin added as new section and to Table 3-2
55, 60
Text added in Table 3-2 and Port CAN pin descriptions about non-
connection of RxCAN pins when MSCAN modules are not used.
Registers 68 FPOPEN bit added to EEMCR register
Flash Memory
116
New paragraph added to overview about flash protection via
FPOPEN bit
117
Last part of FEEMCR opening paragraph changed to ‘if HVEN or
PGM or ERAS in the FEECTL register is set’
120
Changes made to the Flash programming description for
clarification of aligned words
122 New section 7.11 Flash protection bit FPOPEN added
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
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