Datasheet

Clock Functions
Technical Data MC68HC912DT128A — Rev 4.0
182 Clock Functions MOTOROLA
12.8 Clock Divider Chains
Figure 12-6, Figure 12-7, Figure 12-8, and Figure 12-9 summarize the
clock divider chains for the various peripherals on the
MC68HC912DT128A.
Figure 12-6. Clock Generation Chain
REDUCED
CONSUMPTION
OSCILLATOR
PHASE
LOCK
LOOP
EXTAL
XTAL
0:0
SYSCLK
TO
BUSES,
SPI,
PWM,
ATD 0 , AT D1
TO
RTI, COP
BCSP BCSS
SLOW MODE
CLOCK
DIVIDER
EXTALi
EXTALi
EXTALi
SLWCLK
PLLCLK
0:1
BCSP BCSS
1:x
BCSP BCSS
MCS = 0
MCS = 1
÷ 2
÷2
TO
MSCAN
CLKSRC = 1
TCLKs
T CLOCK
GENERATOR
E AND P
CLOCK
GENERATOR
PCLK
ECLK
XCLK
TO
SCI0, SCI1,
ECT
TO CPU
SYNC
MCLK
TO BDM
÷ 2
SYNC
TO CAL
TO CLOCK
MONITOR
CLKSRC = 0
CLKSW = 0
CLKSW = 1
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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